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Latch has enable signal and we cascade latches to make flip flops. How enable for latch converts to clock in flip flop. I mean how and why enable driven latches form edge triggered flip flops. Why Flip flops are not enable driven, but are edge triggered?

Snoke
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  • Clock is connected to 'enable' of cascaded latches. – Mitu Raj Dec 01 '21 at 05:34
  • Perhaps [something like this](https://i.stack.imgur.com/DMdqC.png)? – jonk Dec 01 '21 at 05:59
  • @jonk thanks. I understand the connections and how it is used. My Question is how and why it becomes edge triggered from enable driven latches. – Snoke Dec 01 '21 at 06:03
  • When I see more from you, and feel I better understand how I might be of some help, I may write. Others, though, may already feel able without more. Hopefully so. Just not me, at this time. – jonk Dec 01 '21 at 06:04
  • connect two latches in series ... one controlled by EN and the other controlled by inverted EN ... when first latch is enabled, its output follows the input and the second latch input is disabled ... when EN state changes, the first latch output no longer follows its input ... the second latch follows the output of the first latch (which no longer changes) – jsotola Dec 01 '21 at 06:57
  • Two sample and Holds in series buffered feedback loop with positive feedback is the actual mechanism for CMOS D clocks , unlike 2 gates used as R-S latches. – Tony Stewart EE75 Dec 01 '21 at 13:19

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Processes that only require asynchronous state machines will use RS latches. (wait, react by set OR reset)

Synchronous machines share clocks to trigger on the same edge or opposite edges , so this is for sampled-data systems or edges which define when the data is valid.

Edge trigger avoids the contention when both S&R are active. The response to that condition depends on which releases first.

"Machine" is just a generic term here for some electronic transfer function or logic process.

The actual implementation uses two NMOS/PMOS analog switches a.k.a. two TG's or transmission gate analog switches with CLK and inverted CLK to control the positive feedback. Thus the cascading inverted data or Q.bar sampled and buffered in two latch stages yields a rising edge sensitive CLK.

In other words the dual stage latch CLK rising edge as a HOLD to SAMPLE transition of the 1st stage as it goes from SAMPLED to HOLD state.

enter image description here

Tony Stewart EE75
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The latches in a D flop (or JK for that matter) operate on opposite clock levels. At the ‘active’ edge (rising, say), the first latch is closed as the second latch is open, allowing the first latch data to flow through.

So despite the ‘edge trigger’ name, the pair of latches still work on levels.

There’s a variant D or JK flop design that uses just a latch and a pulse generated from rising clock that opens the latch briefly on the rising edge. This could be said to be truly ‘edge-triggered’. This kind of design, although simpler, isn’t favored in modern logic.

hacktastical
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  • This is not technically incorrect in CMOS .{-1} The edges are used by dual sample and hold complementary FET switches as a S&H with positive feedback on the positive edge only. So they do use edges.and latency of S&H.. So the cascade effect is you use two transmission gates as latches with positive feedback to toggle the 1st to hold then bufffer the result held. – Tony Stewart EE75 Dec 01 '21 at 13:23
  • Um, the open-first then close-first / open second is *exactly* how a TG-based flop works. Same with a mux or a gate type. – hacktastical Dec 01 '21 at 15:45
  • It is the positive feedback tristate in 2 stages that makes it +ve edge sensitive not Level sensitive – Tony Stewart EE75 Dec 01 '21 at 16:08
  • And that follow input / hold feedback in each TG-type latch in a master-slave pair is controlled by a *level*. The feedback can be replaced by a storage capacitor, like in a dynamic flip-flop, but it’s still controlled by a level. – hacktastical Dec 01 '21 at 16:44
  • It's not a static level but a closed loop track and hold edge with PFB. But semantics agree dynamic edges go between 2 static levels – Tony Stewart EE75 Dec 01 '21 at 16:59