Question regarding the MOSFET gate Miller plateau region

Question

During turn of on an N-MOSFET, the gate drive dynamic characteristics curve looks like this:

• The gate voltage across the gate terminal of MOSFET rises linearly for charging input capacitance Ciss until the Miller plateau voltage region. The voltage remains constant until Cdg is discharged with the rate of change of VDS voltage and after that, the gate voltage raises linearly again until the maximum applied VGS voltage across gate terminal.

Why is the gate voltage during the Miller plateau region flat?

I am curious about why the gate voltage during the miller plateau region is flat (what forces the Vgs to behave like that - what are the parameters) gate current during that period is also constant (flat.)

In the Miller plateau region, the voltage is constant or sluggish as Cdg is discharging with respect to VDS voltage change.

Why is Vgs flat? (The reason behind this.)

Answer 1

These tests are done with the gate driven by constant voltage through a resistor, so gate current depends on Vgs and gate resistor. During the time when Vgs is constant, then voltage across the gate resistor is constant, so gate current is also constant.

So, why is the gate voltage flat during switching?...

I've drawn C2, and made it much larger than the MOSFET's Cds, to make the gate-drain capacitance explicit.

So, this begins with the FET in the OFF state, so v(out)=Vds is equal to the supply voltage, and load current is zero. When the driver applies a voltage pulse to the gate resistor, first gate voltage rises to about 3V, at this point the FET turns on.

When it turns on, it runs in linear mode. It isn't fully ON yet, so this is not about RdsON, rather it runs as a common source amplifier, with feedback through C2.

So if we push positive current through the gate resistor R7, Vds increases, which turns on the MOSFET a bit more, so it increases its drain current. This lowers Vds, which causes current to flow through C2 in the opposite direction of the current through the gate resistor. This is negative feedback, and these two currents cancel each other. So if we want Vds to move, we have to push charge C2, which we do by pushing current through the gate resistor.

So what we have is just the same thing as an opamp wired as in integrator, the "-" input of the opamp which brings output voltage down is the gate, and the opamp's output is the drain. The difference is the MOSFET is a transconductance device, so it has a current output, while the opamp has a voltage output, but you get the idea.

During this "integrator" phase, Vgs is pretty constant, and Vds moves.

Once the FET is fully on, it no longer works in linear mode, it's just a resistor, so this feedback system turns off, and we have the next phase of the turn-on which is just charging Cgs and Cds while Vds doesn't move. So, the gate is just a capacitor charged by the driver through the gate resistor which gives an exponential voltage rise just like any RC circuit.

Answer 2

Why is the gate voltage during the Miller plateau region flat?

To understand why \$V_{GS}\$ may be constant while a MOSFET circuit is experiencing Miller plateau, it is important to look at the \$V_{DS}\$ vs \$I_D\$ characteristics for a MOSFET.

If a change in the state of a circuit keeps \$V_{GS}\$ constant, then that change MUST involve moving along a curve of constant \$V_{GS}\$. If the MOSFET is in the saturation region during this change of state, then \$I_D\$ must stay fairly level. If \$I_D\$ were anything but fairly level during this change in circuit state, then it would necessarily be the case that \$V_{GS}\$ was not fairly level during that change.

The circuits that manufacturers use to find typical gate-charge \$(Q_G)\$ vs gate-voltage \$(V_{GS})\$, typically control \$I_D\$ and keep it constant during the Miller plateau phase. For example, in this circuit from Infineon / International Rectifier's IRFZ44 Datasheet, the subcircuit in the dashed box serves to hold the lower MOSFET's drain constant during the Miller plateau phase.

Not all circuits will hold \$I_D\$ constant. As a result, the Miller plateau may be sloped. An example is this circuit with a resistive load instead of a current limiter.

^{simulate this circuit – Schematic created using CircuitLab}

Here, the Miller plateaux are more or less "linear" or straight, but they are not horizontal. The lower the resistance of R1, the greater the slope of the Miller plateau.

A similar incline of the Miller plateau occurs when the MOSFET drain is connected to an inductive load.

^{simulate this circuit}