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I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki:

Modern 64-bit processors such as designs from ARM, Intel or AMD are typically limited to supporting fewer than 64 bits for RAM addresses. They commonly implement from 40 to 52 physical address bits13 (supporting from 1 TB to 4 PB of RAM). Like previous architectures described here, some of these are designed to support higher limits of RAM addressing as technology improves. In both Intel64 and AMD64, the 52-bit physical address limit is defined in the architecture specifications (4 PB).

Crucial site, understanding-cpu-limitations-with-memory talks about speed only, point to Intel site. But as far as I know, info e.g. i7 tells 32Gb because at time of creating the processor only 16Gb modules was available, meaning it supports 2 modules only (2 modules is my guess now, wiki quote above talks about bits).

I'm only starting to understand technical details how memory works, like ranks. What exactly prevents all modern e.g. Intel processors to claim to being able to address as least 1Tb (per wiki above)?

Is the reason same for ARM in smartphones? E.g. 875:

Max size 24 GB

For ARM I have no experience changing amount of memory as all my devices had SoC, though I recently found ARM should have systems with modules, as web search indicate (e.g. https://www.anandtech.com/show/13635/apacer-launches-32bit-sodimm-for-arm-risc-v-systems).

Martian2020
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    @DKNguyen. why do you claim they are wrong? Not 40 bits (cause 40 bits is ~ 1TB)? Can you provide a link to support that? P.S. I've fixed the title. – Martian2020 Nov 21 '21 at 04:10
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    Oh wait, I forgot that each byte has an address, not each bit. So a 40-bit address can address 2^40 bytes in which case it really is 1TB, – DKNguyen Nov 21 '21 at 04:19

2 Answers2

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Your quote from Wikipedia is referring to physical address space, the size of all memory addresses available to the processor. It is just the sum of all addresses that can fit into physical memory space. However, not all physical memory is RAM. PCIe devices like GPUs, flash storage, etc also occupy physical memory addresses which are used to communicate with them or copy data to/from them. For this reason the physical memory address space should always be larger than the largest possible amount of RAM in the system. If it isn't you end up with situations where not all hardware can be installed at the same time or not all memory can be accessed, as actually happened in the old days of 32 bit x86.

So clearly if your system is well designed, a 40 bit address space does not imply that you can actually have 2^40 bytes of RAM. If it did you would lose access to your PCIe and other hardware. What actually limits your available RAM then? The memory controller on your CPU has to actually be able to map physical addresses to unique cells of RAM. There is a practical limit to how much memory it can actually access. Individual DIMMs have a maximum size set by the specification, and the memory controller itself has a maximum number of memory channels.

For example, a 10th generation Intel Comet Lake processor supports up to 4 DIMMs, with a maximum size of 64 GB per the DDR4 spec. Thus the maximum possible capacity is 256 GB (although Intel says only 128 GB so perhaps 64GB DIMMs are not actually supported). The remaining physical address space can still be used by other hardware, just not by the memory controller.

user1850479
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  • For Cornet Lake - do you mean to say that processor has set of direct "wires" in motherboard from its grid array to each memory slot/module separately? if so, that is basically the answer to my question as pertains to x86. – Martian2020 Nov 21 '21 at 04:17
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    @Martian2020 In this particular processor there are 2 memory channels and up to 4 DIMMs, so pairs of DIMMs share wiring. But yes, the CPU is connected to memory via a memory controller which maps physical addresses to cells in the DRAM. – user1850479 Nov 21 '21 at 04:21
  • To put it more correctly (not editing as maybe have been read): processor has certain number of sets of ball grid connections to connect to each module? – Martian2020 Nov 21 '21 at 04:21
  • @Martian2020 And each address pin on the package needs routing on the silicon wafer to actually function. – DKNguyen Nov 21 '21 at 04:22
  • I know modern processors have integrated memory controllers, please clarify about ball grid physical layout / limitations. – Martian2020 Nov 21 '21 at 04:22
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    It is both the package and inside the package. That's why I said "and" (I meant for it to chain onto your previous comment about the BGA.) – DKNguyen Nov 21 '21 at 04:23
  • " 2 memory channels and up to 4 DIMMs". What prevents to design a motherboard (that would function with that processor "correctly") with shared wiring to put e.g. 16 DIMMS? – Martian2020 Nov 21 '21 at 04:38
  • Intel ark site claims only 32GB support, but 4 DIMMS with 64GB max per DD4 specs (from wiki) = 256. Can 8550U support 256GB? – Martian2020 Nov 21 '21 at 04:41
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    @Martian2020 You're limited by what the memory controller supports. Intel will sell you processors that support 16 DIMMs, but they cost more. – user1850479 Nov 21 '21 at 04:44
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    @Martian2020, you can only share a single memory channel between two DIMMs because of signal integrity (for the most part), and memory clock frequency is limited by distance to the furthest IC. – Simon Richter Nov 21 '21 at 04:45
  • @Simon, thank you. I would appreciate a link to a video explaining how data ends (and starts) on a particular DIMM (of a pair) and why we cannot have e.g 4 of DIMMs shared this way, or short explanation of the tech mechanism. – Martian2020 Nov 21 '21 at 04:51
  • @Martian2020 This is getting pretty far off topic, but see this page for an overview of how DDR4 works: https://www.systemverilog.io/ddr4-basics – user1850479 Nov 21 '21 at 04:58
  • Why off-topic? twice more DIMMs twice more RAM. – Martian2020 Nov 21 '21 at 05:04
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    @Martian2020, the DIMMs in a channel are connected in parallel on the data and address/control lines, but receive separate Chip Select and Clock Enable signals. From a digital logic perspective, this could be scaled to more DIMMs, but this degrades signal quality to a point where you have to reduce clock frequency, so the problem is on the analog side. – Simon Richter Nov 21 '21 at 05:05
  • @Simon, are Chip Select produced in the processor / package? If so, than it is a limitation and part of the answer to OP. – Martian2020 Nov 21 '21 at 05:14
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    @Martian2020 Yes, the chip select signals come from the memory controller. IMO if you want to get into the details of how DDR4 works, you should edit your question (or post a new one) rather than continually ask me. That way more people see your question. – user1850479 Nov 21 '21 at 05:21
  • Thank you for the suggestion of a new question! – Martian2020 Nov 21 '21 at 05:41
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Supporting more memory isn't free. It requires supporting more addresses which requires more circuitry which requires more space on the die and more pins on the package which will probably lead to a bigger package which decreases yield and increases cost. Why do it if you don't need it?

DKNguyen
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  • can you provide details? cause most of processors have less then 40 bits? If so, please add links to examples of (preferably) Intel i7 spec sheets something. – Martian2020 Nov 21 '21 at 04:13
  • Thank you for correcting my English :-) When I'm typing quickly I sometimes become less accurate than usual. (than and then is my particular problem, know of some rule to tell when to use e or a?) – Martian2020 Nov 21 '21 at 04:27
  • I know the meaning difference, I forget when to put e or a. – Martian2020 Nov 21 '21 at 04:31
  • Whoops. Made a mistake in my post. Here it is again: "Cause" is a different word than "because". When you speak orally to say "because" you actually are speaking 'cause, with the apostrophe. It's not something that needs spec sheets. The question is very similar to asking "why isn't every car built to be the maximum size that would still allow it to be street legal?" – DKNguyen Nov 21 '21 at 04:31
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    *Than* is only used for comparisons. *Then* is used the rest of the time. So only use the 'a' if you are comparing something. Use 'e' the rest of the time. – DKNguyen Nov 21 '21 at 04:31
  • Oops, again my English, I meant not "rule", but something like a https://en.wikipedia.org/wiki/Mnemonic, however that it a question for another SE site. Thanks again! – Martian2020 Nov 21 '21 at 05:50