It is a very simple question but it made me think. I have been working on finite state machines. I came to topic of finite state machines from combination circuits. In the book it says that sequential circuits which uses register with same clock input prevent race condition since it is synchronous design.
My question, is there a possibility that the clock cycle is so fast, delay on the circuit causes race condition?
A race condition is a situation where a signal is divided into two or more paths, and depending upon whether it traverses one path faster or slower than another path, the results could be different.
Given this definition, if a race condition exists, then it does not matter how fast or slowly signals change in the circuit, the race condition will still exist.
There are circuits that technically have race conditions in their logic that are, nevertheless, extremely reliable. This reliability is achieved by strict control over the timing delays in the circuit. If the manufacturing process is such that one path is guaranteed to "win", the race condition will not have adverse effects.
There are other circuits that technically have race conditions in their logic that are reliable if the signals supplied to these circuits obey given timing restraints, for example set-up and hold-times for data inputs for registers.
Excessive clock speeds will almost certainly make those circuits unreliable. However, technically, it is not that the excessive clock speeds "create a higher risk of a race condition", but that they create a higher risk that an existing race condition (i.e. a situation where different propagation speeds along different paths will result in in different outcomes) will have unwanted outcomes.
