I'm trying to simulate a MOUSETRAP asynchronous pipeline for FPGA. For the control stage, I need to implement the following circuit:
DELAY is a delay element which I have correctly implemented using inverters.
For this I have written the following VHDL code:
entity control is
port(Ri, Ao: in bit;
L, Ro, Ro_nd: out bit); -- Ro_nd: no delay
end entity control;
architecture behavior of control is
signal Ro_ndx, Lx: bit := '0'; -- intermediate signals
begin
Lx <= (Ri and (not Ao) and (not Ro_ndx)) or ((not Ri) and Ao and Ro_ndx);
Ro_ndx <= (Lx and Ri) or ((not Lx) and Ro_ndx) or (Ri and Ro_ndx);
L <= Lx;
Ro_nd <= Ro_ndx;
delay: work.delayelem port map(Ro_ndx, Ro);
end architecture behavior;
According to what I can see in the RTL Viewer, it appears to have been synthetized correctly. However, when I run the timing simulation in Quartus II (using ModelSim), Ro_nd is XXXXX until Ri is activated, but it is meant to be zero.
As a consequence, L doesn't work as intended. I suspect it has to do with the fact that Ro_ndx is a feedback signal/wire so its initial value is being treated as XXXXX despite my attempt to initialize it (with := '0'). How can I fix this?
Extra info: Using Quartus II 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition; Device: Cyclone IV GX EP4CGX15BN11C8.
