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In my current FPGA design, I have a fast clock that has to travel to multiple locations inside the device.

Among those locations, I have a set of 2-flip-flop synchronizers for clock-domain crossing purposes to pass signals to slower clock domain.

Since most of the resets in my design are driven as synchronous resets, every time I run timing validation the tool shows it failing at the reset stage.

I was wondering if I could use the 2-flip-flop synchronizers without reset. From what I've found so far, that seems to be the case.

nanoeng
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1 Answers1

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The synchronizer doesn't need a reset to perform its synchronization function.

However, if it is important at system startup to avoid unintended signals then a reset will be needed.

Of course, if implementing the logic in an FPGA you may want to initialize the registers just to avoid the first few clock pulses being unknown in the simulation. Depending upon the logic the whole simulation could be "unknown".

Kevin White
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    One additional point: The reset signal can help prevent unwanted optimization behavior. At some point I had the synthesis insisting on implementing such a FF chain as LUT-based shift register, which doesn't have the intended timing behavior. A reset was the easiest way to prevent this optimization. – asdfex Nov 03 '21 at 15:34
  • @asdfex - Interesting, I've never seen that. – Kevin White Nov 03 '21 at 18:31