Hold time constraint equation

Question

I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint

Hold time constraint is defined as:

tccq + tcd ≥ thold

tccq is the minimum delay from the time the clock rises till the output Q of the flip flop reacts to the rising clock edge.

Similarly tcd is the minimum delay from the time input Q changes till the output D of the combinational logic changes.

1. I am confused about the hold time constraint equation and need some help understanding it - I would expect thold ≥ tccq, as Q will not react before tccq and a thold ≥ tccq would ensure that Q has reacted to the input.
2. Moreover, according to the constraint equation, thold cannot be greater than tccq + tcd, but I don't understand why can't thold be greater than tccq + tcd?

Answer 1

tccq is a characteristic of the first flip-flop and it means that after the rising edge, its output will change after tccq.

thold is a characteristic of the second flip-flop and it means that after the same rising edge, its input must remain stable for thold so that its output can have the time to be refreshed (setup).

tcd is the delay induced by the combinatorial logic between the output of the first flip-flop and the input of the second flip-flop.

At the rising edge of the clock (assumed the same for both flip-flops) the second flip-flop must refresh before its input changes which means its thold must not exceed tccq + tcd.