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I'm working on an eighteen-layer board right now. Almost all of the signal layers have high-speed, single-ended traces that should run up to 15 gbit/s. The vias for these high-speed traces will be backdrilled to be a total length of 23 mil, keeping the via stubs no longer than roughly 1/20th of a wavelength. However, to keep costs down, there are only two drill pairs, meaning that a high-speed signal may only need to travel 3 mil down a 23 mil via. In this worst-vase scenario, the via would have a 20 mil stub, which my calculations indicate is less than 1/20th of a wavelength. This will minimize reflection caused by the stub.

However, I am unsure how to calculate the via impedance of stub. According to the Saturn PCB Toolkit, via height will non-negligibly affect impedance at such high frequencies, but this can easily be adjusted by changing the anti-pad diameter. But should my calculations account for the length of the via that the signal would actually travel (3 mil), or should the calculations still account for the entire 23 mil of via height?

Calculating antipad based on via signal length:

Calculating antipad based on via signal length

Calculating antipad based on total via height:

Calculating antipad based on total via height

wisner
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    Won't the untraveled portion of the vias create a small stub on both ends of the via? And won't that small stub just add some capacitance to that part of the trace, that needs to be accounted for when calculating the impedance of that part of the trace? – SteveSh Oct 26 '21 at 19:57
  • Guess what I'm saying is what you have is transmission line->small cap -> 3 mil via -> small cap -> trans line? – SteveSh Oct 26 '21 at 19:59
  • The signal would be traveling from the top layer into some internal layer, which could potentially leave a stub of up to 20 mil. – wisner Oct 26 '21 at 20:05
  • I'm starting to think I might be able to approach the issue by analyzing the via as a T-network, essentially modeling it as stacked vias where there's only one annular ring... Gonna try that tomorrow. – wisner Oct 26 '21 at 20:07
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    @wisner at this frequency, using Saturn PCB for via modeling is kind of impressive and pitiful. Above 3-5GHz you need a 3D full-wave analysis software to model via impedance. Also at your speed you also need to model stitching vias, I don't really know how you do it. Doing 18L board with 15Gbps signal means you have some money, so either you buy a simulation software, either you spend your money on multiple board spin. Hyperlynx got its price down for few years now, and you can still rent it. You also have Simbeor that is relatively cheap for SI simulation. – zeqL Dec 15 '21 at 22:00
  • @zeqL we unfortunately have the drive and ambition, but we don't have the money for the simulation software right now. I think I'm going to need to talk to my folks and insist that simulation software is the only thing that's going to keep our cost down in the long run, especially since we intend for faster boards in the future. I appreciate the advice! – wisner Dec 20 '21 at 19:15
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    @wisner I did several design with 10G/12.5G without much simulation tbh. But currently our boards use a Intel/Altera via structure (with antipad) given in AN766 (high-speed design guidelines). At least you can try to rent ou buy a limited time license to keep cost low and simulate a lot of structure that you could reuse after. That need a lot of preparation to be useful. – zeqL Dec 21 '21 at 18:17
  • I'll see what I can do. I've pretty much followed the Xilinx high-speed guidelines, and I've studied their own eval-board architecture, but even using a trial of a software, it's a headache to get it approved for use on our systems :'( Thank you! – wisner Jan 04 '22 at 18:51

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I would input the physical parameters of the vias once back drilled.

Try another program and then compare the 2 results.

It's an interesting question.

Enrico Migliore
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    Is there another free program you would recommend? I'm afraid I don't have access to any 3D simulation tools. Could you make a suggestion for a free program? – wisner Oct 26 '21 at 19:20
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    I haven't been simulating RF structures since 2016 and I actually don't know if any free or open source simulator. You may download a free trial version of ADS or Microwave Office. – Enrico Migliore Oct 26 '21 at 19:59