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I am not an EE student but a CS student, so I may not have in depth knowledge regarding the specific of latches, flip flop.

The answer to this question was:

Q(next)  = (RC + (Q'))'
Q'(next) = (SC + Q)'

I am having trouble getting this answer as my final answer I derived (by using K-map) was: Q' = S + R'Q. I have no idea how "C" is derived. I believe "C" is related to the clock cycle of the circuit.

How should I go about in deriving the answer?

Math.anony
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    SR has no clock contrary as D or JK flipflops. so here I guess what you call a Clocked SR is in real a D then yes C here is in my opinion the exact time the clock rises from "0" state to "1" state. –  Oct 26 '21 at 05:07

2 Answers2

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Clocked latch is IMHO and oxymoron. It it's clocked it's a flip flop, if it's not clocked is a latch, at least in all the books I've seen.

However your formulas RC and SC suggest some kind of clock gating. As you tough it's the trick to make it to work with a clock.

In the simplest implementation C is the clock itself. When the clock is high the latch switches assuming that neither S and R changes during the high phase of the clock.

In a more useful implementation C is the egde of the clock. This is not something that can be expressed in boolean logic. The idea is that C is true if and only if the clock signal is rising.

The realization relies on the reaction time of the physical logic gate (the propagation delay). Lots of info in this question/answer

Rising edge pulse detector from logic gates

Remember however that the true synchronous alternative to S/R is the J/K since it doesn't suffer from the anomaly asserting both S and R. There are uses for the R/S but it's simply inferior (except for complexity)

Lorenzo Marcantonio
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You probably want to think about this as two cascaded stages:

The second stage is probably a coupled NOR gate S/R Latch. See: https://www.youtube.com/watch?v=kt8d3CYWGH4

The first stage are two AND-gates serving as an input enable gated by the clock(C). This makes it so that the S/R latch inputs go from an inert phase (both inputs 0) on the latch to an active phase on the latch (S&R pass through).

Putting them together converts an S/R latch into an S/R flip-flop clocked on a rising edge. See: https://www.youtube.com/watch?v=HZg7fNu-l24&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm&index=150

Hope this helps.

Andrew Lentvorski
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