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I am trying to implement a square wave generator with a specific output frequencies (15 - 45 kHz) but I've encountered a problem, the 0.5 V/μs slew rate. From what I've researched the main component that can change it is the 30 pF capacitor but even when I bring it down to 1 pF in LTspice it doesn't make much difference and I don't think is "healthy" for the circuit to just change this value to whatever I need. How can I change the values or even the circuit do get a higher slew rate?

enter image description here

I want to build a circuit with real components, I can use any op amp I want as long I have the internal circuitry so I can modify parameters, play with it, etc.. The reason I choose 741 is because I have the internal circuitry and it was the easiest to understand (mostly the subcircuits of it). What I really want to know is how can I change the circuitry to have a higher slew rate.

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PowerTb321
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    Could you please read this answer: https://electronics.stackexchange.com/questions/304521/reasons-not-to-use-a-741-op-amp/304522#304522 and then explain why you would use the 741? Also explain in a broader sense what you're trying to achieve. Is this just a "design exercise" in LTSpice or do you want to build a circuit with real components? If you want to build it, there's no point messing (with the internals of) the 741 because it is an IC, you cannot change what's inside. – Bimpelrekkie Oct 24 '21 at 20:16
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    *How to improve slew rate of LM741* You would not, you would use a different opamp. The 741 is ancient, you should use a more modern opamp anyway. – Bimpelrekkie Oct 24 '21 at 20:18
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    The capacitance is internal to the op-amp so you can only change it by changing the op-amp. – Justme Oct 24 '21 at 20:22
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    You said you were using LTspice but the screen shot is of Falstad. Explain exactly what model of the 741 you are using and how you are running the simulation. – Elliot Alderson Oct 24 '21 at 20:42

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You know linear \$dV/dt = Ic/C \$ when large signals are current limited such as Op Amps .
And 10% to 90% step \$dV/dt = 0.35 / f_{-3dB~ BW}\$
And \$GBW = Av * BW_{-3dB} \$

You have encountered a problem with SR=0.5V/us. That is equivalent to a BW of 0.35 / 0.5 V/us = 700 kHz.

~ The Falstad web sim. is fast in simulation, but only models the Vbe vs Ic with an hFE variable and not the Miller Capacitance. When you go through inverting amplifier stages, the phase shift adds up. When you have higher than a 2nd order slope at unity gain, the way to make it unity gain stable is to add a 1st order integrator inside the loop to make it a 1st order loop at unity gain. This 30 pF does that. However removing the default 30 pF would eliminate the slew rate in Falstad's, but 1pF (DOES NOT. Try 1 fF, not 0) as the current is low in the path of this capacitor, thus equivalent to a high impedance or RC time constant.

~ LTSpice, which simulates far slower but uses a more complex model for each capacitor. This makes little difference, if you compensate it as such ( with a bigger one than all the rest combined from each stage) but will, if you remove the cap in this > OP Amp> Internals model simulation.

~ Also remember that Falstad's will use an Ideal Op Amp with zero input offset,Vio and zero Zout and thus infinite current-limit and slew rate but gain limited gain (default = 1e5) for input error gain. So when necessary add 200 ohms in series with output before the negative feedback (NFB) for realism as NFB lowers the Zout by design. We would call this a Level 1 simulation and the 741 internals model a Level 2 in complexity of the model characteristics.

~ The lowly diode and transistor has many levels of complexity for each model described elsewhere in this channel. Stay tuned-in and search.

Keep in mind, your load and all parasitic capacitance, inductance, and ESR for every component including traces, connectors, and cables and include those estimate when using Falstad.

Here I assumed an extremely small lithography perhaps with a saphire substrate, such that the transistors had negligible capacitance and by increasing input bias current, and reducing the 30 pF to 1 pF , the 741 now has 100 MHz BW ! (lol)

enter image description here

Using Labelled Nodes, the Feedback resistors are added for 60 dB gain and the input Vio is approx. +60 uV. So you can see the capability of the 741 is not from schematic design but the performance of each transistor.

I can sell these to @Audioguru if he wants to order 100k. ;)

Tony Stewart EE75
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Reducing the value of the 30pF capacitor should increase the slew rate but will also reduce stability margins making the op amp potentially less stable by increasing open loop gain with a resulting increase in loop gain.

Another way, I would suggest to increase slew rate is to reduce the value of the 5k resistor which will increase the current in the current source of the first stage making more current available to charge the compensation capacitor which will increase its maximum rate of charge. But be aware that this will also increase open loop gain and loop gain with a resulting reduction in stability margins.