VHDL Error (Simple Expression Expected)

Question

I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the two since we are supposed to use don't cares for inputs that will not happen.

The code is basically supposed to give the same output for either 2's complement input or offset binary. So, for instance, decimal number 7 is "1111" in offset binary and "0111" in 2's complement. Both forms should generate an output of "1111100000" depending on the value of the switch oe ('1' for offset binary, '0' for 2's complement).

I've debugged my code as much as I can at this level and I do not understand what I'm doing wrong.

Active-HDL is currently giving me errors at lines 48 and 55. I'm getting two "simple expression expected" errors.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity pitch_decoder_2 is

    port(d, c, b, a : in  std_logic;
         ob         : in  std_logic;
         led        : out std_logic_vector(9 downto 0));

end pitch_decoder_2;

architecture myarch of pitch_decoder_2 is

    type tbl is array (15 downto 0) of std_logic_vector(9 downto 0);

    constant table : tbl := (
        "1111100000",                   --  7
        "1111100000",                   --  6
        "1111100000",                   --  5
        "1111100000",                   --  4
        "0111100000",                   --  3
        "0011100000",                   --  2
        "0001100000",                   --  1
        "0000100000",                   --  0
        "0000110000",                   -- -1
        "0000111000",                   -- -2
        "0000111100",                   -- -3
        "0000111110",                   -- -4
        "0000111111",                   -- -5
        "0000111111",                   -- -6
        "0000111111",                   -- -7
        "0000111111");                  -- -8

    signal input : std_logic_vector(3 downto 0);
    signal tmp   : std_logic_vector(2 downto 0);
begin
    input <= std_logic_vector' (d, c, b, a);
    tmp   <= std_logic_vector' (c, b, a);

    with input select

        led <= table(to_integer(unsigned(d & tmp)))
        when "0000" | "0001" | "0010" | "0011" |
        "0100" | "0101" | "0110" | "0111" |
        "1000" | "1001" | "1010" | "1011" |
        "1100" | "1101" | "1110" | "1111"
        and ob = '1',

        table(to_integer(unsigned(not d & tmp)))
        when "0000" | "0001" | "0010" | "0011" |
        "0100" | "0101" | "0110" | "0111" |
        "1000" | "1001" | "1010" | "1011" |
        "1100" | "1101" | "1110" | "1111"
        and ob = '0',

        "----------" when others;

end myarch;

Also, if you have any tips on how I can improve the code while maintaining the assignment instructions, please feel free to suggest anything.

as a side note: I would not use the `qualified_expression` expressions (e.g. `tmp <= std_logic_vector' (c, b, a);`). Keep a, b, c and d as different signals. Don't glue them together in a new kind of type. — vermaete, Feb 25 '13 at 15:44

score 4 · Accepted Answer · 2013-02-25T17:14:04.240

with input select 
    led <= table(to_integer(unsigned(d & tmp)))
    when "0000" | "0001" | "0010" | "0011" |
         "0100" | "0101" | "0110" | "0111" |
         "1000" | "1001" | "1010" | "1011" |         
         "1100" | "1101" | "1110" | "1111"
         and ob = '1',
    ...

The syntax error occurs at the "and" clause which is not part of a valid "select" choice list.

However note that the "when" expression is equivalent to ignoring the "input" altogether so

 with ob select 
     led <= table(to_integer(unsigned(d & tmp))) when '1',
     ...

You may be under the misapprehension that explicitly specifying all combinations of '0' and '1' values for "input" excluded any input values containing 'X', 'U', '-' etc (of these symbols, only one is a "don't care").

Indeed in simulation it may actually work; however a little thought will show that there is no synthesisable hardware primitive that can reliably do so, and unless you are writing a testbench, this is certainly the wrong approach altogether and the simple syntax error is the least of your problems.

EDIT : here's one way (untested) using both a table and a selected signal assignment, using don't cares to reduce the table size. Some further simplification may be possible.

architecture myarch of pitch_decoder_2 is

        type tbl is array (3 downto -4) of std_logic_vector(9 downto 0);

        constant table : tbl := (  
        "0111100000",  --  3
        "0011100000",  --  2
        "0001100000",  --  1
        "0000100000",  --  0
        "0000110000",  -- -1
        "0000111000",  -- -2
        "0000111100",  -- -3
        "0000111110"); -- -4

        signal sel : signed(3 downto 0);

begin

        sel   <= (d xor ob) & c & b & a;

        with sel select led <=
           "1111100000" when "01--",
           table(to_integer(sel)) when "00--" | "11--",
           "0000111111" when "10--",
           "----------" when others;

end myarch;

So I know in an actual hardware design, I shouldn't get 'X', 'U' or '-', but I'm not understanding how not specifying all possible binary inputs rules out those combinations when compiling. — audiFanatic, Feb 25 '13 at 15:42
Also, I replaced that stuff with your simplified version and I'm still getting the same error on lines 44 and 45. pastebin.com/Qe9ZvC5s — audiFanatic, Feb 25 '13 at 15:46
yes ... your select values are boolean expressions, not std_logic values — , Feb 25 '13 at 16:22

vermaete · Answer 2 · 2013-02-25T15:54:20.560

0

You have all possible combinations of input in the when, so you can remove that code. What stays is 'if ob='1' or '0'`

led <= table(to_integer(unsigned(d & tmp))) when ob = '1' else table(to_integer(unsigned(not d & tmp)));

Note there is no ob = '0' anymore. A signal is or '1 or '0'. (Okay, this is not true, but you could grab the idea...). So, if it's not '1', it's '0'.

edited Feb 25 '13 at 15:54

answered Feb 25 '13 at 15:31

vermaete

380
3
15

Although this will work it doesn't satisfy the stated constraint, which is to use a selected signal assignment. This is a conditional signal assignment. – Feb 25 '13 at 16:37

score 0 · Answer 3 · answered Feb 25 '13 at 15:34

0

I think you might be a little confused about how the operators "|", "and" and "=" work, and their relative precedence. Perhaps adding some parentheses to clarify your meaning will help.

answered Feb 25 '13 at 15:34

Dave Tweed

168,369
17
228
393

VHDL Error (Simple Expression Expected)

3 Answers3