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I am working on a piece of hardware design verification, which includes CPU(ARC), Design( containing AHB), and SRAM connecting to the AHB bus. I want to know if CPU can do burst write on the SRAM via AHB bus. If yes, how to implement it.

Here are some details of my work:

connection CPU -> AHB -> SRAM

C code

//piece of C code to write 4 DWs into the SRAM
wr(add0, DW0)
wr(add0+4, DW0)
wr(add0+8, DW0)
wr(add0+12, DW0)

The above C code do only single write to the SRAM via AHB.

In order to do burst write, what should I consider about?

Should I refer to the ARC manual for a burst function? Or add some FLAGS to compiler to optimize it to a burst operation? Essentially I want to know how does CPU implement the burst write.

Tom Ma
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  • The manual should have the answers. Also pay attention to whether the DMA controller can issue bursts, even if you can't burst via the instruction set. –  Oct 01 '21 at 20:55
  • Thanks for your reply. I do see the CPU manual mention DMA channel to do burst. If there is no instruction set for burst, I wonder that how CPU can use DMA channel launch a burst write. – Tom Ma Oct 01 '21 at 21:01
  • Generally by writing to the DMA controller registers. –  Oct 01 '21 at 21:02

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