How does CPU control implement pipeline stall

Question

The original question was deemed lack of focus. This post is specifically about cpu pipeline stall.

How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during instruction fetch? Specifically,

1. Does the cache controller have to determine a hit / a miss within a single CPU cycle and have a signal connected to CPU control to inform hit or miss and CPU control has to setup all the necessary stall signals to data path pipeline within the same cpu cycle? During the next cycle, CPU then disables PC register from updating in next clock cycle to keep the in-flight read address stable until it's fulfilled? Then CPU sends "bubble" down the pipeline. How could a "bubble" / NOP be implemented exactly in a pipeline?

2. Does cache controller inform CPU that a read is finished by some strobe signal to CPU control? since a read miss could take arbitrary long time.

Answer 1

Oliver, you seem to be conflating a number of fundamental concepts all together. This is why you are getting pushback as your question lack focus and to give a meaningful answer would be difficult.

First up, 'synchronous microarchitecture' are fluff words. So let's concentrate on cache miss and pipeline stall.

A cache miss won't necessarily cause a pipeline stall - these are two separate mechanisms.

For the pipeline, think of a car production line. For whatever reason, incoming parts (instructions) are not available. What happens to the production line? It stalls. What does this entail? Nothing moves on the production line. Time is wasted. Obviously this is something we want to avoid due to inefficiency.

The idea of the cache is to anticipate what memory is going to be accessed and keep a fast, local copy. For our car production line example, the cache is the local store of parts (instructions). When that local store is depleted, then the next request is going to be a miss. Simply we have to wait until we get another shipment from main memory. This means our production line stalls.

Note that a pipelined processor doesn't necessarily involve a cache and a cache doesn't necessarily require a pipelined processor. This is why you want to simplify your scope.

in summary:

1. The cache controller can take as long as it wants. In reality, we use a cache for a performance increase so we want it to be a fast as possible. 1 clock? maybe, but that's implementation dependant. It should be faster than a main memory access otherwise there would be no use for the cache.

What the the cpu do when it stalls? send a 'bubble' down the pipeline? Again, that's implementation dependant. The simple answer is ' the cpu does no useful work'.

As for the PC (program counter), that doesn't necessarily update each clock. Once again, implemenatation dependant.

2. Does the cache controller inform the cpu when the memory request is satisified? Yes. There clearly needs to be some mechanism for this to occur. How else would the cpu know to continue? If the main memory cycle time was fixed, maybe we could assume X clock cycles and no need a handshake. Implementation dependant.