11

I've been studying CMOS logic gate design, such as an inverter here:

enter image description here

Why do we need the N-channel MOSFET at the bottom at all? Couldn't it be replaced with a simple resistor into ground like this?

enter image description here

Soumil
  • 697
  • 2
  • 11
  • 4
    CMOS is not the only logic : your second circuit is called PMOS logic, which was quite common in the early-mid 1970s. My first digital alarm clock was PMOS. –  Sep 28 '21 at 12:02
  • It's funny that the resistor approach of PMOS seems natural. For me, originally learning about this stuff, the concept of dumping current through a resistor to get logic sounded horrifying, like a horrifyingly bad solution to a confounding problem, and when I learned about CMOS it was like OMG MAGIC! – R.. GitHub STOP HELPING ICE Sep 28 '21 at 22:26

6 Answers6

24

Couldn't it be replaced with a simple resistor into ground like this?

Yes it can and is has been done:

PMOS logic

there's also the complementary version:

NMOS logic

We've been there and done that! So why are we almost exclusively using CMOS these days?

Think about the situation when the PMOS or NMOS (in PMOS or NMOS logic) is switched ON. Then a current flows. That current flows all the time until you switch the MOSFET off.

On average in a large design, I would expect half the transistors to be switched on and the other half to be switched of. With many transistors, that's a lot of current!

That means, a lot of power is consumed.

That means that large and complex NMOS / PMOS logic chip will get HOT.

This is solved when using CMOS logic as the resistor is replaced with another MOSFET that will be off so no current can flow. Only when you use a CMOS circuit at high speed will it consume more current. When a CMOS circuit is in a static state (does not change), it consumes almost no current (only some leakage current).

Another advantage is that a MOSFET can have a very low resistance when it is on, much lower than a resistor. OK, you can make the resistor's value lower but then what happens to the current when the MOSFET is switched on? Yes, an even larger current.

So CMOS logic is much more power efficient and can also be much faster for the same amount of power that is used.

As we can only dissipate a limited amount of power in one IC, CMOS designs can also be much more complex than NMOS or PMOS logic designs.

So why does NMOS / PMOS logic exist? At the time when these technologies were used, CMOS was not invented yet and/or the fabrication process was too expensive to make a competitive IC. Later, CMOS technology was (cost) optimized and became the standard choice of IC technology that it is today. So NMOS / PMOS logic are simply no longer needed for new designs.

Bimpelrekkie
  • 80,139
  • 2
  • 93
  • 183
  • 2
    I think it's also noteworthy that many of the earliest complex logic chips were PMOS designs. This is because PMOS fabrication was somewhat simpler than NMOS. For example the Intel 4004 as well as the Rockwell PPS-4, two of the very earliest microprocessors, both used PMOS. By the time Intel introduced the 8080 NMOS processing had been developed far enough that using that design was feasible. – jwh20 Sep 28 '21 at 11:09
  • 8
    One more thing you didn't mention is that a FET likely takes less die area than a resistor and therefore costs less. (Or else the resistor might actually just be a FET that's only partially turned on) – The Photon Sep 28 '21 at 14:47
  • Please don't mind me asking a follow up question, but if you could, why does fast switching contribute to heat in CMOS? – Aditya Sep 28 '21 at 21:43
  • 1
    Fast switching = more current, more current = more heat – John Doe Sep 28 '21 at 23:18
  • 2
    @Aditya When a CMOS logic cell switches state, there's a short time (like a nano second or less) when both the NMOS and PMOS conduct. That shorts the supply, OK not exactly short (zero Ohms) but it does draw current from the supply. If your circuit operates at 1 Hz this happens once per second: you'd hardly notice. If your circuit operates at 1 GHz it happens 1 Billion times per second resulting in a significant current and power dissipation in the chip. – Bimpelrekkie Sep 29 '21 at 06:51
  • CMOS switching causes the lines and loads being driven to be charged or discharged. The power is shed as heat in the FET, which has an on resistance. This is called *dynamic power*, and is expressed as frequency x capacitance x V^2. More here: https://computationstructures.org/lectures/tradeoffs/tradeoffs.html – hacktastical Sep 30 '21 at 05:28
  • @Bimpelrekkie Not just that, but also the current involved in switching; the current that charges and discharges the gates. – Hearth Oct 04 '21 at 04:25
4

In the early days of MOS (and, indeed, bipolar logic) they did exactly that: used only one type of transistor and used a pull-up or pull-down resistor built in silicon to achieve the opposite state. This was an economical way to make logic that used fewer process steps, in a time when extra process steps were very expensive (they’re still not cheap, but the advantages of complementary types justify the cost, as we’ll see below.)

What you’ve drawn in your second diagram is more or less what PMOS logic looks like. As it so happens, PMOS was the first popular MOS logic (c. 1964) on the market, until NMOS became viable once certain manufacturing issues (materials purity) specific to NMOS were solved.

What’s the matter with PMOS? PMOS transistors are inherently slower than NMOS due to their use of holes as a majority carriers vs. electrons in NMOS (electron mobility is much higher than hole mobility, by about 2.5x). PMOS also requires a larger transistor size for equivalent drive capability. So once NMOS became practical, PMOS’s days were numbered.

With the larger adoption of NMOS (c. 1971), PMOS shifted to being promoted as a low-power alternative and so continued to find use in consumer and military applications, until it was fully supplanted by NMOS. NMOS itself gave way to CMOS in the mid-1980s.

In both PMOS and NMOS, the passive ‘resistor’ is constructed from a depletion mode device, while the active FET is enhancement mode. Depletion mode FETs have a default-on threshold, so that when Vgs = 0 the device is conducting. This pull-up (or -down) depletion-mode FET also has its channel width and length adjusted so that its on resistance is about 5x of the enhancement mode FET.

So what’s the problem with that resistor? You may have noticed that the PMOS pFET inverter is sourcing current when the pFET is pulling the line high: current is flowing through the FET to the pull-down. This uses power even when the inverter isn’t doing anything. This is called static power consumption, with ‘static’ meaning ‘not changing’. NMOS has the same issue when driving out a low: the nFET is sinking current.

Compare the CMOS inverter. When outputting a logic high the pFET is on, but the nFET is off, so no current flows. Same thing when outputting a low: nFET on, pFET off, no current flow. This allows CMOS to have theoretically zero static power consumption. That’s a huge win, and worth the extra process steps to make it just by itself.

CMOS is also faster due to the use of active enhancement-mode FETs in both directions instead of a weakened depletion-mode pull-down (pull-up for NMOS.) For these two reasons and some others (like simpler biasing) CMOS is the dominant logic used today.

Nevertheless, sometimes the passive pull-up / pull-down approach is useful for solving certain problems, such as level shifting, constructing wire-OR logic or implementing shared buses like I2C.

hacktastical
  • 49,832
  • 2
  • 47
  • 138
  • There is still ECL and PECL out there in active use (It is very useful when doing FAST IO where we don't really care about the power burned). – Dan Mills Sep 28 '21 at 18:15
  • I can't think of a modern I/O standard that uses either PECL or ECL. LVDS (PCIe, SATA, USBB3) or CML (HDMI) seem to dominate these these days. – hacktastical Sep 29 '21 at 01:05
  • PECL is popular in applications like high speed converter clocks because it typically has lower additive jitter then LVDS. – Dan Mills Sep 29 '21 at 10:20
  • 2
    Out of curiosity, what were those manufacturing difficulties with NMOS that you mention? – Hearth Oct 04 '21 at 04:26
  • Honestly, I couldn’t find an authority on it. – hacktastical Oct 04 '21 at 05:59
  • I found this, from here: https://en.wikipedia.org/wiki/Depletion-load_NMOS_logic "However, pMOS transistors are relatively easy to make and were therefore developed first — ionic contamination of the gate oxide from etching chemicals and other sources can very easily prevent (the electron based) nMOS transistors from switching off, while the effect in (the electron-hole based) pMOS transistors is much less severe. Fabrication of nMOS transistors therefore has to be many times cleaner than bipolar processing in order to produce working devices. " – hacktastical Oct 05 '21 at 00:16
3

A Mosfet always has a voltage drop associated with it. So if you want to switch within the full boundaries (V+ <-> V-) you need both channels. If you are okay with the voltage drop on your output signal (V+ - x) you are good to go. But think about cascading. This effect worsens with the number of sequential arrangements.

ElectronicsStudent
  • 2,746
  • 5
  • 18
  • 1
    What do you mean by "always has a voltage drop associated with it" and how is this relevant? The OP has not proposed a source follower. – Elliot Alderson Oct 04 '21 at 12:47
2

Every trace has some capaticance C. Resistor from your example will form lowpass filter with cut-off frequency fc=1/2PiR*C. Lower R gives highier cut-off frequency. Lowest R you can achieve with MOSFET. It's just allow you to speed up switching.

ufok
  • 323
  • 1
  • 6
  • *Lowest R you can achieve with MOSFET.* A short has a lower resistance. RC time would be even faster with a low valued resistor as a result. – tobalt Oct 04 '21 at 06:32
  • @tobalt don't forget we are talking about logic gates - output has to be in one of two states: LOW, near negative rail and HIGH, near positive rail. Look at OP's picture from the question: to drive output HIGH, PMOSFET must have Rds(on) << R (<< means much less - lets say Rds (on) = 1/10R). Using NMOSFET instead of R you can achieve 10 times faster switching. – ufok Oct 05 '21 at 05:44
0

I've been studying CMOS logic gate design

Were you aware that the "C" in "CMOS" stands for "complementary". This means that CMOS is designed to use two "complementary" transistors so, when you say this: -

Why do we need the N-channel MOSFET

You are missing the point of what "complementary" means. A bit like 0% alcohol beer.

Andy aka
  • 434,556
  • 28
  • 351
  • 777
0

One thing to also take note of is that resistors in an IC layout are HUGE, compared to MOSFETs. And considering that high resistance values are recommended when using MOSFETs, they're kind of a waste of space too.

The first image is a 2 MOhm resistor and the second one is a CMOS Inverter in comparison.

enter image description here http://webpages.eng.wayne.edu/cadence/ECE6570/res/Layout_of_Resistor.htm

enter image description here http://pages.cs.wisc.edu/~david/courses/cs755/cs755/tutorials/tutorial3/tutorial3.html

thisjt
  • 73
  • 1
  • 9