Defining a variable in bytes using Verilog

Question

I am trying to implement a 16byte input (K) in Verilog which I have never done before. Also, I need to pull each byte from the index K using a for loop. In this case, b=16bytes, w=32bits, u=w/8. Here is the for loop pseudo code I took from the RC5 encryption paper:

for i = b - 1 downto 0 do:
   L[i/u]=(L[i/u]<<8)+K[i];

Here is my attempt in Verilog. I am also having trouble telling the for loop to decrease from 15 down to 0 in steps of 1.

module RC6_KeyScheduler( in, clk, out );
input byte [0:7] K[0:15] ;        // Input should be 16bytes  
input clk;
output reg [0:127] out;   

parameter b = 16;
parameter w = 32;                 // word length in bits 
parameter u = w/8;
parameter c = 4;

integer i;

reg [0:31] L[0: c-1];       

//<statements>

always@ (*)
for (i = b-1, i>-1; i=i-1)
begin
    L[i/u] = (L[i/u] << 8) + K[i];
end    
    
endmodule

Right now I am getting errors on the way I am defining my input K and on my inequality in my for loop.

Any comments on how to fix my Verilog code to match the pseudocode would be appreciated.

Why do you have `[0:7]` after the `byte`? And doesn't `i` need to be a `genvar`? — Dave Tweed, Sep 22 '21 at 16:56
@DaveTweed That was my attempt at defining a 16 byte input. I added the [0:7] since there are 8bits in a byte. I'm not sure what the correct syntax would be — PrematureCorn, Sep 22 '21 at 17:40
@DaveTweed why does i need to be genvar? I have never used that data type before — PrematureCorn, Sep 22 '21 at 17:45
I would like to add just some suggestions towards the configurability of your code after observing RCA algorithm: `parameter c = b/u ;` , `reg [0 : w-1] L [0 : c-1] ;` , `input [0 : 7] K [0 : b-1] ;` — Mitu Raj, Sep 22 '21 at 20:34

toolic · Answer 1 · 2021-09-22T18:41:28.270

I got this helpful error when I tried to compile the code on the VCS simulator:

input byte [0:7] K[0:15] ;        // Input should be 16bytes  

Error-[SV-PDNA] Packed dimensions not allowed
  Packed dimensions not allowed on type 'byte'.
  Packed dimensions are only allowed on types resolving to single bit types 
  (reg, logic or bit), packed arrays, packed structures, and packed unions.

You should either drop the byte keyword (which declares an 8-bit type) or [0:7].

I got another error because your port list did not match your port declarations because K is missing from the list. You can simplify this by using ANSI style declarations which I will show below. There is no need to maintain 2 lists.

I got another error on your for statement: you need a semicolon instead of a comma.

Putting this all together, the following code compiles without errors for me:

module RC6_KeyScheduler (
    input [0:7] K [0:15] ,        // Input should be 16bytes  
    input in, clk,
    output reg [0:127] out
);

parameter b = 16;
parameter w = 32;                 // word length in bits 
parameter u = w/8;
parameter c = 4;

integer i;

reg [0:31] L[0: c-1];       

always @(*)
for (i = b-1; i>-1; i=i-1)
begin
    L[i/u] = (L[i/u] << 8) + K[i];
end    
    
endmodule

Perhaps the simulator you are using does not give you errors for all these cases. Or, perhaps the error messages are not clear enough. You can sign up for a free account at edaplayground, where you will have access to multiple simulators. Sometimes you can get more helpful error messages with different simulators.

Defining a variable in bytes using Verilog

1 Answers1