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I am trying to overclock my STM32F303VC. Unfortunately I can't due to a HARD FAULT EXCEPTION. Could you help me to find the error?

I also attached the code.


    RCC->CR|=1<<16;
  while(((RCC->CR)&(1<<17))!=(1<<17));//HSEON
  
    RCC->CFGR|=(1<<18)|(1<<19)|(1<<20);//PLLMUL

    RCC->CFGR|=(1<<13);//PPRE2
    RCC->CFGR|=(1<<10);//PPRE1
    RCC->CFGR|=(1<<8);//PPRE1

  
    RCC->CFGR|=(1<<16);//PLLSRC
  
      RCC->CR|=(1<<24);
  while(((RCC->CR)&(1<<25))!=(1<<25));//PLLON
  
  
  RCC->CFGR|=(1<<1);//SWS E SW

  while(((RCC->CFGR)&(1<<3))!=(1<<3));

enter image description here

JRE
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mattia flagiello
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    It is usually better to post code as text rather than as a picture. – JRE Sep 16 '21 at 17:41
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    It's not called overclocking if you are trying to use a part that is rated to work at 72 MHz at a rate of 72 MHz. Please let CubeMX or CubeIDE to generate a working clock init for you. There is no need to put energy into re-inventing the wheel, when you could just write your application code. – Justme Sep 16 '21 at 17:57
  • Thanks so much for the explanation, unfortunately I need to write this code myself for an exercise. Thanks a lot anyway – mattia flagiello Sep 16 '21 at 18:05
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    Again, use CubeMX to generate the code. Copy as required. It will work you through the settings. – StainlessSteelRat Sep 16 '21 at 18:39
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    Save your sanity (and ours) by using the bit-mask definitions when you configure the registers. A line of code like `RCC->CFGR |= RCC_CFGR_PPRE2_DIV1` is far easier on the eyes than `RCC->CFGR|=(1<<13)` for example. – brhans Sep 16 '21 at 21:08
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    And in addition to the above, what's conspicuously absent from your code snippet is something to configure the Flash Latency. If you want to run the HCLK at 72MHz you have to configure the Flash for a latency of 2 wait states (FLASH_ACR register, [ref manual](https://www.st.com/resource/en/reference_manual/rm0316-stm32f303xbcde-stm32f303x68-stm32f328x8-stm32f358xc-stm32f398xe-advanced-armbased-mcus-stmicroelectronics.pdf) page 78) *before* raising the bus clock. Overclocking the Flash is almost guaranteed to cause HardFaults because it'll be giving the core invalid instruction code to execute. – brhans Sep 16 '21 at 21:11
  • Also ... you're only ever 'or-ing' bits into RCC_CR and RCC_CFGR. You're imagining that all the bits in those registers are already 0's which is not a safe assumption. You need to ensure that the bits you expect to be 0's actually are 0's too. – brhans Sep 16 '21 at 21:16
  • Thank you very much by correctly configuring the flash latency the problem has been solved.Thank you again. – mattia flagiello Sep 17 '21 at 06:45

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