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a) Suppose a binary pick-up adder (carry-select) of 32-bits, comprising 4 sub-sections adders spreading carry of range 8 bits. Show the values ​​obtained internally in the circuit of this adder to perform the addition of the numbers 01011001101100111110110011001101 and 10010110011111000001101100110110. Specifically, show the input and output values ​​on each 1-bit full adder circuit, as well as the input and output values ​​on all multiplexers in the circuit. If each complete 1-bit adder circuit and each multiplexer circuit cause a delay of 2T in the execution of the operation, where T is the delay time of an elementary gate, find the calculation time of the retained output.

b) Repeat the above if the 32-bit adder includes 6 sub-sections adders spreading carry, ranging in order from less to more important sections 2, 4, 4, 6, 6, and 10 bits.

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The idea of that method is :

The adder is divided into two halves of equal length. And for both halves, the addition is started at the same time. In the left (more significant) half we don't know whether the carry input of the rightmost full adder is a 1 or a 0. Therefore, we do the addition of the left half twice at the same time, once with a 0 at the carry input and once with a 1. If the right half with its addition is done, we know the incoming carry of the left half. So we know which of the results is the right one, which we then select (select). The other (wrong) result is simply discarded.

Is that correct?

So we split 01011001101100111110110011001101 into a_1=0101100110110011 and a_2=1110110011001101, right?

And we split also 10010110011111000001101100110110 into b_1=1001011001111100 and b_2=0001101100110110, right?

Then we add a_1+b_1 wih carry 0 and a_1+b_1 wih carry 1.

We also calculate the addition a_2+b_2.

As for the addition a_1+b_1 wih carry 0 : $$0101100110110011+1001011001111100=1111000000101111$$

As for the addition a_1+b_1 wih carry 1 : $$0101100110110011+1001011001111100=1111000000110000$$

As for the addition a_2+b_2 : $$1110110011001101+0001101100110110=0000100000000011\ \ \text{ with carry } 1$$ So we select the second case of a_1+b_1.

Is everything correct?

How could we continue?

Mary Star
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    I see this was just deleted from [here](https://math.stackexchange.com/questions/4251333/carry-select-adder-time-calculation). What is a *propagation spreader*? Is this a carry look-ahead circuit? – jonk Sep 16 '21 at 05:30
  • It is a carry-select circuit. I edited a bit the text at this section you mentioned, I hope it is clearer now. Is my attempt correct so far? @jonk – Mary Star Sep 16 '21 at 08:03
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    That's much clearer, now. Thanks for the addition and I feel I understand the question better, now. However, I have to say that I'm having trouble reading the rest of what you write. It might help if I saw a diagram. It's your writing of *"And we split also ..."* that throws me off, I admit. I'm not sure I'm following you at this point in time. Regardless, I'll +1 your question now. – jonk Sep 17 '21 at 07:16
  • I thought that we have to split the given numbers into two halves, I named the two halves of the first number a1 (the part from the beginning, i.e. the left part) and a2 (the right part). I named the two halves of the second given number b1 and b2 (again b1 is the left half and b2 the right half). Then we add a1 and with b1, i.e. the two left parts. We add them twice, once with carry 0 and once with carry 1. At the same time we calculate also the sum of a2 and b2, then we know the carry of this addition and so we can take the respective result of the addition of a1 and b1. @jonk – Mary Star Sep 17 '21 at 07:53
  • I tried to do that, I don't know if my attempt is correct. What kind of diagram should I make? Or what should I change so that my attempt is clrearer to understand? @jonk – Mary Star Sep 17 '21 at 07:53
  • Or am I thinking wrong? @jonk – Mary Star Sep 17 '21 at 19:17
  • Based on your explanation, that is actually correct. I think what @jonk meant is you can color code the binary numbers so that it's easier to know which binary split you are adding up. Even I had to double-check which variable of the split is the left one or the right one. You can keep splitting it more and more, depending on how many adders you have. – thisjt Sep 23 '21 at 12:21
  • @MaryStar There are two parts in your question. The first is about delay times in some particular circumstance. But you don't write much about that, so I think it is more about the second part. Here I didn't see you discuss the muxes required and their arrangement. I have my own thoughts about what is being asked there. But you didn't clarify that for me. [This is what I have in mind](https://i.stack.imgur.com/VR43I.png) but I've no idea if it is appropriate to your question because I just don't know if I understand it well enough. – jonk Sep 23 '21 at 20:11

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