Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?

Question

Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?

Answer 1

Thanks for sharing the information. I enjoyed reading it.

I am no match for Nyquist, Shannon, or the authors of your reference documents. And, I thought I had to interpret x1.5 in a little different way. I forgot how I did, but I will try to explain. Please do not down vote or alter this, so we can promote independent thinking.

---

When Metastability is concerned, clock has the maximum of 1/2 cycle time for setup + hold, to be recorgnized as an edge, either rising or falling. Thus, rising edge is valid at a certain time after a valid falling edge, and vice versa. And we may apply the same setup and hold time to other signals in the Metastability perspective.

Thus, a signal from a clock domain's minimum residency is 1/2 cycle time of the clock. Let's the clock to be cycle time of Tcy, and the frequency of Fcy. And, we will analyze how a clock (domain) samples a signal from another clock domain.

When a signal was sampled (n0) at the earliest moment, 0xTcy, of the valid signal, the next sample (n1) window comes in duration of W1 from the current sample point,

1xTcy < W1 < 1.5xTcy --- (1)

When a signal is sampled at the latest moment, 0.5xTcy, of a valid signal, the next sample window comes in duration of W2,

W2 = W1 - 0.5xTcy => 0.5xTcy < W2 < 1xTcy ---(2)

Thus, the sampling frequency, f1, of window W1 is:

(1 / 1xTcy) > f1 > (1 / 1.5xTcy) ---(3)

The sampling frequency, f2, of window W2 is:

(1 / 0.5xTcy) > f2 > (1 / 1xTcy) ---(4)

From the relation of 1xTcy = 1/Fcy:

1xFcy > f1 > (1xFcy / 1.5) ---(3-1)
2xFcy > f2 > 1xFcy ---(4-1)

However, the reluctant sampling of 1.5xTcy misses sampling moment in the following cycles (n2, n3, ...). And, apparently;

A sampling window can be caught only by more than one shots (sampling) per a cycle. --- (5)

In order to find how many shots are needed, Let's call multiple of f1 fm1.

fm1 = f1 x M ---(6)

Now, eq(3) can be converted to:

(1xFcy x M) > (f1 x M) > (1xFcy / 1.5) x M ---(3-2)

From what we have found in (5), the lowest frequency has to be 1xFcy, or a shot per cycle. This leads to:

1xFcy = (1xFcy / 1.5) x M, and M = 1.5 ---(7)

Which resolves eq(3) to:

1.5xFcy > fm1 > 1xFcy ---(3-3)

Applying M to eq(4),

3xFcy > fm2 > 1.5xFcy ---(4-3)

The intersection of eq(3-3) and eq(4-3) occurs at 1.5xFcy, which tells;
Minimum of 1.5 times faster clock is required to sample a signal from another clock domain.

---

Concept of maximum setup and hold time for a clock domain.

Concept of signal residency and interval, compared to clock cycle.

Early alignment: f1, W1, and fm1.

Late alignment: f2, W2, and fm2.

Answer 2

There is no speed limit. They can be any ratio <=1. The 1.5x factor assumes the slow clock is perfectly 50% d.c. or 010101.

Consider only the fundamental freq. with the requirement being ; 1) no missing or extra cycle counts (or glitches). You must sample at least 50% faster, assuming the slow clock is perfectly 50% duty cycle.

Shannon's Theorem says you need 2x f to sample a sine fundamental to detect that frequency, but you do not recover the phase or amplitude perfectly, only detect that fundamental exists. Here, we sample with an edge and reset with an edge if about the same speed to detect if the slower input is high at least once during that interval. You won't get duty cycle or harmonic content. The 2 state single FF satisfies the Shannon criterion in the case of widely separated frequencies. Whereas, a dual FF edge trigger is used for “almost synchronous” or pleisiochronous clocks.

If a slow clock or bit of information clocks a 1 into a flip-flop and at any time that output is sent into a much faster bit stream, it resets the flip-flop at the same time as the read output latch to ensure it is always sent only once.

Anecdote. I used this method in '77 to send dual Servo Motor currents as digital bits using a voltage controlled one-shot as a 1kHz max tachometer signal into a 10 Mbps bit stream. It was sent some slow spare status bits, to get real-time feedback but with lower Bandwidth from a nuclear reactor to the control building over coax. It served to monitor servo friction in a robotic SCADA custom design I once did. (long time ago, far,far away) It appeared very accurate on analog edge-meters on the console. Without that async to sync, there were aliasing effects.

Answer 3

There is nothing special about the value of 1.5x. The author goes on to explain what he means a few paragraphs further down:

[This will work,] as long as the signal generated in [one] clock domain is wider than the cycle time of the [other] clock [...] A safe rule of thumb is the signal must be wider than 1.5x the cycle width of the destination clock

I.e., it must be guaranteed that the receiving clock is at least a little bit faster than the clock the signal originates from. In theory, 1.0001x would be good enough, but there are always sources of error:

• all flip-flops have a setup and hold time, i.e. the signal must be stable for a certain time, often many percent of the cycle time. If the pulse is short, we might miss the setup time requirement in one cycle and miss the hold time requirement in the next cycle, effectively missing the whole pulse.

• Oscillator frequencies vary with temperature and voltage and it's not guaranteed that both clocks vary in the same way and by the same amount throughout all operating conditions.

• Clocks have jitter, i.e. clocks generated by a PLL can have period variations of 100 ps, which can easily be a couple of percent of the total clock period.

• Switching times of flip-flops and all the transistors encountered during routing are not homogeneous. The transition time from high to low can well be different to the one from low to high. This results in the signal (that should be active for exactly one clock cycle) to be active for less or more than one clock period.

• Switching thresholds of each and every transistor in the circuit is not equal, some may have a higher threshold and effectively shorten the length of the pulse.

• All routing inside the chip depends strongly on the temperature and the current operating voltage in this specific location of the chip. If there is a lot of activity from other signals, voltage may drop locally and alter rise times and propagation delays, leading to a distorted signal length.

As a result, the receiving clock domain must be "quite a bit" faster than the source domain. A factor of 1.2 might be on the safe side, if operating conditions are favorable and the clock speeds are not close to the maximum the chip can deliver. I would be quite cautious if my clocks were this close in frequency and give the design a thorough test. With the cited factor of 1.5x you'll be on the safe side in any current FPGA no matter what happens. (Exceptions exist, e.g. ASICs built in custom processes can exhibit uncommon behaviors.)