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I am using Synopsys Design Compiler for synthesizing my design. I have read in the User's guide of DC that by default it assumes ideal clocking during synthesis meaning that clocks have zero network latency. However, when doing post-synthesis functional simulation I can see that the rising edge of the clock observed on clock pins of registers has 4ns delay (compared to clock source).

Here is how I create the clock in my tcl script for the Design Compiler:

create_clock clk -name CORE_CLK -period 25 -waveform {12.5 25}
set_drive 0.0 [get_ports clk]

Here is a warning I get during the synthesis which might be related to this issue:

Warning: Design contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) Net 'clk': 2469 load(s), 1 driver(s)

Does anyone know why that is happening?

O'ara
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  • there must be 'maximum fanout' for timing analysis set some where in the tool, it's exceeded for your design. That's the warning (I am guessing, am not expert in asic design) – Meenie Leis Aug 17 '21 at 16:28
  • Depends what you are synthesising for. In ASICs, clock tree synthesis is a big thing; in FPGAs you're usually stuck with whatever the built-in dedicated clock nets give you. –  Aug 17 '21 at 18:20
  • So what is your actual question? Is it about the warning or about the delay on clock you stated earlier? Better if you could elaborate with timing report or so. – Mitu Raj Aug 17 '21 at 19:41

1 Answers1

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You need to distribute your clock signal with a proper clock distribution network. You need to use a series of inverters, with progressively stronger drive strength, to buffer the clock. Ideally you would divide the design into quadrants and use an "H-tree" clock distribution scheme. Try searching for "H-tree" for examples and more information.

Of course, this will introduce latency in the clock signal. To deal with this, all branches of the clock tree should have approximately the same delay length and all flip-flops should be clocked from the leaf branches of the tree.

Elliot Alderson
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