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I have been asked this question in an interview, and I wondered what the correct answer was and why. What should you power on first in an FPGA? Is it the Core Logic, I/O blocks, or the memory?

MarkU
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Zarif Rahman
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    Maybe they were more interested in hearing what you'd bring to the table when examining the question (monotonicity, tracking, etc.) as well as how you would go about working through details (min and max ramp times, order, etc.), referring to added information found in datasheets. In short, what you know generally and what you also know should be sought in info provided by a manufacturer. Maybe not looking to hear a "one size fits all" answer? Just a thought. – jonk Aug 16 '21 at 00:31
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    I'd do what the datasheet tells me. I think I/O tends to be last though to prevent nonsense logic from being driven. It's hard to go wrong just ramping up everything at the same V/s which makes the lowest logic power up first (usually the core logic). Minimizes the voltage differential between all rails and all that back current business. – DKNguyen Aug 16 '21 at 00:33
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    Here’s some interview advice I’ve been given before that may be helpful. Employers will often ask questions they don’t expect you to know the answer to so they can see how you respond. If they see you trying to come up with something that you don’t know the answer to, they may be worried you will do that in your job instead of asking for help which is what you should do. In the future, if you don’t know the answer to an interview question, just be honest about it, give it a try but tell them you’re not sure and that you’d like to know the correct answer. Just my 2 cents. – Ryan Aug 16 '21 at 01:12
  • I felt really clueless when I was asked this question. I did get the vibe he was probing me to go deeper but I said core logic and he moved on to a different question. @jonk Would you mind delving into a bit more of what you mentioned? Monotonicity and tracking is something I have never heard of and would like to read more. I don't think we went over anything like this for undergrad. – Zarif Rahman Aug 16 '21 at 01:12
  • @ZarifRahman Look up "regulator sequencing". You wouldn't learn this in undergrad because you barely build anything in undergrad. It's something you do when building a real circuit that can misbehave under real world conditions. You run into it fairly quickly as soon as you start working with ICs that have more than one power supply. – DKNguyen Aug 16 '21 at 01:15
  • They may be looking to see if you have practical knowledge of these kind of devices, or at the very least, if you’ve thought about the problem. As an interviewer I’d be suspicious of a designer claiming to have FPGA knowledge yet not knowing how to design a power supply for one. – hacktastical Aug 16 '21 at 01:16
  • I don't know the answer to this question myself. But when I have interviewed people I am happy to hear them just talk about how they would solve the problem if they don't know. "I would check the data sheet to see what the requirements are" or "I would probably contact application support" or "I assume it is core logic, memory, IO, but I am not sure" or "I would copy a reference design." All of these would show you are not going to get stuck on it, but follow some course of action to resolve what you don't know. – user57037 Aug 16 '21 at 01:26
  • This has been, I hope, an educational set of comments for the OP. Put together well, I think this would compose a very, very good answer. @mkeith comment is also a nice addition to the others -- something I've personally experienced in spades at a day-long interview at a gaming company. They posed a problem they hadn't yet solved and one their entire business hung on. I spent the entire day talking about what I could bring to the problem and how I'd approach working towards a solution. Had a job offer the very next morning. – jonk Aug 16 '21 at 02:06
  • Every FPGA datasheet has "power sequencing" section. – Mitu Raj Aug 16 '21 at 08:40
  • They don't always use that name for it though, at least in the Cyclone V documentation the relavent section is titled "hot socketing" and says "The hot-socketing circuitry monitors the VCCIO, VCCPD, and VCC power supplies and all VCCIO and VCCPDbanks.You can power up or power down these power supplies in any sequence" – Peter Green Aug 16 '21 at 14:05

2 Answers2

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The answer depends on the chip, so the best answer is whatever the manufacturer recommends in the datasheet.

There’s several things to consider:

  • latch-up, which would give preference to I/O first, then core power
  • power spikes, which would give preference to core first, then I/O
  • undefined I/O behavior, which gives preference to core first, the I/O

Why are there differences between chips? It depends on the I/O cells and how they interface to and from the core. Different processes and libraries will have specific sequence requirements.

For their part, FPGAs have very sophisticated pads compared to most ASICs, being designed to support a wide range of voltages and I/O standards, including per-bank power-down. FPGAs come up de-configured so their I/Os have to be well-behaved, more so than typical ASICs. The pad configuration state comes from the bitstream loaded into the core, and the pads are 'turned on' when the loading completes.

It follows then that the voltages that the FPGA supplies involved in bistream loading (core, control) have to come up before (or at least, the same time as) I/O to allow configuration to happen. Xilinx has a specific supply for configuration-related I/Os that needs to be enabled at the same time as the core.

That said, the devices I’ve worked with (various Xilinx) want the core supplies turned on first. The reason given is to minimize power spikes, but this isn’t a hard requirement: no damage will happen if I/O comes up first.

Artix example here: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Artix-7-Power-Up-Sequencing/td-p/420619

Power‐On/Off Power Supply Sequencing

The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.

hacktastical
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  • slew rate of the rails as well. A3P and co needed core and I/O brought up at the same rate (with CORE before IO iirc), again its the datasheet and whitepapers for the specific devices –  Aug 16 '21 at 01:17
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First of all, since it’s an interview question there is no ‘correct’ answer. They are paying attention to the way you answer, and how you analyze the question to arrive at the answer.

The thing that jumps out at me is that the logic uses both inputs/outputs as well as memory, and may end up stuck in a fault state if those are not available on startup. So logic is last, and there may be other gate logic using I/O so I would do that first. Memory second because whatever, that should have power when the logic is finally on

EE1337
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    I used to think that way too but the reason I/O isn't first is because it can drive nonsense with no logic to control it and damage or disrupt things connected to it. – DKNguyen Aug 16 '21 at 02:05
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    @DKNguyen Depends on chip. One chip (not FPGA though) had a requirement to power up I/O before core, because otherwise the core starts up with default settings, as the pull-up/pull-down resistors used on IO pins could not be read if the I/O supply is not present - If you did use default settings then the power up sequence did not matter as long as it was fast enough. – Justme Aug 16 '21 at 07:06
  • @Justme Interesting – DKNguyen Aug 16 '21 at 13:18