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I'm writing some code in Verilog with a 6502 soft core. After not getting the results I expected, I realized the problem was that I needed to reset the 6502 (by asserting the reset line for 2 cycles) before it would start working.

This got me thinking: How do digital logic circuits know they've been powered on for the first time and that it's time to initialize? In other words, if the 6502 isn't smart enough to realize that it's been powered on and should start processing, how does the thing that resets the 6502 know?

Are flip-flops guaranteed to be zero when power is applied? Can the hardware check some "initialized" flip-flop for zero?

Could the hardware use an RC circuit to detect the power-on event by allowing to detect an initial 0 volts and then eventually some threshold voltage as the capacitor charges?

Willis Blackburn
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    The voodo of supervisory circuits intended to operate when there is not enough voltage to operate. And latches. – DKNguyen Aug 15 '21 at 18:06
  • @DKNguyen Please consider removing duplication flag. I see something else. – jay Aug 15 '21 at 18:20
  • @jay Huh? What? – DKNguyen Aug 15 '21 at 18:21
  • @jay I closed it because I think the other question did address the same subject. Do you think there's something missing? – Willis Blackburn Aug 15 '21 at 18:29
  • @DKNguyen, no offense I mean. I know it is your privilege, but I would ask you favor to watch a little longer how it develops, please. In my opinion, Wills' question is starting from a different base from the [previous question](https://electronics.stackexchange.com/questions/132066/ics-powering-on-with-random-values), – jay Aug 15 '21 at 18:30
  • @WillisBlackburn thanks, I probably am incorrect. Sorry DKNguyen. – jay Aug 15 '21 at 18:31

2 Answers2

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It is, indeed, common practice to use an RC circuit to hold a Reset input active for a short time after power is applied. There are reset/brownout detect ICs that will generate a reset pulse when power is applied.

Flip-flops and RAM memory will generally be in a random state after power-up, unless reset.

Peter Bennett
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That is very much valid and interesting question, and not too much of surprise to you, other EEs (at least me) find that need as well.
I know you are not talking about external reset nor the internal brown-out. In fact, in my faint memory, some of the FPGA supplies "reset" and "brown-out" detection that you can use it as the input and conditions.

Regardless of that convenient reset and brown-out, the problem of that moment was that, my code had to figure out the initialization status in the code (VHDL).
What I did was: Compare a series of register/memory bits with unlikely can happen patterns, ex. 0xaa55a11900d.

jay
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