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I am required to test how a design behaves if it is run with extremely fast clock frequencies (higher than the maximum frequency allowed by timing constraints). The goal is to detect what kind of faulty behavior could be observed by increasing the operating clock frequency. I have noticed that when I increase the clock frequency to more than a certain value, the clock signal observed at registers in the design remains at X and doesn't change at all. Does anyone know why that is happening?

FYI:

  1. I change the clock frequency in the testbench with which I am testing the design.
  2. When I am running simulations, I use the .sdf file generated from the synthesis phase to get accurate timing information.
  3. I am using Synopsys VCS Simulator to run the simulations.
O'ara
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  • Are you changing the frequency in your FPGA simulation? Or is this real hardware? – Aaron Aug 12 '21 at 17:59
  • Not sure what useful information you trying to derive as the behaviour could be unpredictable and not reproducible. The 'Xs' on simiulation are due to possible metastability caused by timing violation of your design (setup/hold). – Mitu Raj Aug 12 '21 at 18:01
  • What you are seeing is the sort of faulty behaviour that you'd expect if the clock is too fast. Why SHOULD they change? – Russell McMahon Aug 13 '21 at 10:35

1 Answers1

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I suspect you are toggling the clock faster than the clock distribution network can properly change states. The simulation is trying to tell you that the design won't work if you do that.

Don't expect the simulation to give you accurate answers to "what happens if I exceed the maximum clock frequency". Logic simulators typically don't even try to correctly model behavior when timing constraints are violated; you will just get unknown logic states and values. This makes sense, because the actual behavior of the circuit will depend heavily on variations in temperature, supply voltage, and manufacturing. You should accept that the results are truly unknown.

Elliot Alderson
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