Syntax error in SystemVerilog based UVM testbench

Question

I have been getting the following syntax error on compilation-

** Error: (vlog-13069) ** while parsing file included at testbench.sv(2)
** while parsing file included at mypackage.sv(11)
** at dpram_if.sv(1): near "dpram_if": syntax error, unexpected IDENTIFIER, expecting class.

File: dpram_if.sv

interface dpram_if(input bit clk_A, clk_B);

    parameter ADDR_WIDTH = 5;
    parameter DATA_WIDTH = 8;
  
     //port A
    logic [DATA_WIDTH-1:0] datain_A;
    logic [ADDR_WIDTH-1:0] addr_A;
    logic wr_enA;                      //LOW=READ,HIGH=WRITE
    logic enA;                         //ACTIVE LOW
    logic rst_A;                       //ACTIVE HIGH
    logic [DATA_WIDTH-1:0] dataout_A;
     //port B
    logic [DATA_WIDTH-1:0] datain_B;
    logic [ADDR_WIDTH-1:0] addr_B;
    logic wr_enB;                      //LOW=READ,HIGH=WRITE
    logic enB;                         //ACTIVE LOW
    logic rst_B;                       //ACTIVE HIGH
    logic [DATA_WIDTH-1:0] dataout_B;
  

  clocking dut @(posedge clk_A or posedge clk_B);
    default input #1 output #1;
    input datain_A, addr_A, wr_enA, enA, rst_A, datain_B, addr_B, wr_enB, enB, rst_B;
    output dataout_A, dataout_B;
  endclocking
  
  clocking tb @(posedge clk_A or posedge clk_B);
    default input #1 output #1;
    output datain_A, addr_A, wr_enA, enA, rst_A, datain_B, addr_B, wr_enB, enB, rst_B;      input dataout_A, dataout_B; 
  endclocking
    
  modport DUT (input clk_A, clk_B, clocking dut);
  
  modport TB (input clk_A, clk_B, clocking tb); 
  
endinterface

I am a beginner in this domain so any help or advice will be appreciated regarding the issue, please let me know if more information is required.