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I've noticed that on some PCBs, there are some undulating tracks.

An example can be seen on the Compute Module IO for Raspberry Pi Compute Module 4 (CM4).

Compute Module IO Board, PCB Track Example

Apparently, these are high frequency tracks.

What is the function of these ripples? How do I calculate these ripples for the design of my boards containing high frequency communications?

I would like to know more about it, so I can research it.

I am developing a board containing the CM4. So maybe I have to use that kind of trail.

Thank you

Edit:

As I understand it, the main function of corrugation is to make all tracks with a certain function have the same length.

We must add the corrugation where the problem starts. If we don't, the differential impedance designed for the board fails.

Cristian Pastro
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High speed differential tracks must be equal path length end to end in order to prevent propagation skew in differences , in this case on the other side. This is often done for DDR memory.

But this example would have sub-optimal crosstalk with the same gap pair and adjacent tracks, but may be a non-issue for synchronous data.

It could also be overkill for a difference in path length of 20 picoseconds.

Tony Stewart EE75
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  • Good point - that image is definitely not a good example. If there is a trace length difference, it should be corrected near the part that causes the difference. Otherwise the bit edges do not travel in alignment and there is some skew which can degrade the signal somewhat. It could cause some common mode, which could again be battled with a common mode choke. – Justme Jul 27 '21 at 18:12
  • I would not expect the meander position in the entire path length to matter. – Tony Stewart EE75 Jul 27 '21 at 19:14
  • Maybe, but if wires of the pair begin a length difference, and it is compensated somewhere else later, then during that length difference, an impulse that runs ahead of the other wire in the pair no longer experiences the designed differential impedance as the countering signal comes in late. Propagation delay in FR4 is about 6.67 ps/mm. As this is HDMI, it requires intra-pair skew of 0.15*Tbit. Tbit at 6Gbps is 167ps and so max skew is 25ps, or 3.75mm. A difference of 25mm would align edges of consecutive bits, although that is unrealistically large difference. – Justme Jul 27 '21 at 19:37
  • So you are saying that meandering affects differential impedance even when the single-ended impedance to ground plane is constant? Are the jogs away from the other signal path that significant in Zdiff compared to prop skew eliminated. Hmmm that’s why I thought meander position on bottom or top wouldn’t matter. (Say to correct a shorter right angle path on other side) @Justme – Tony Stewart EE75 Jul 27 '21 at 20:15
  • I don't know how significant that is, but in high speed design you always get warned about this in appnotes. The characteristic differential impedance only happens when a positive and negative signal travel at same location so they cancel out in the middle. For PCIe, the differential impedance is 100 ohms, and single ended impedance is 60 ohms, so common mode impedance is 30 ohms. So for some reason, the single ended is not 50 ohms. – Justme Jul 27 '21 at 20:38