There is something called Assertion based testbenches. I am not aware of what they are or if they are possible in VHDL.
But in any case, is it a good practice to sprinkle assertion statements in RTL VHDL code? Or perhaps, have blocks/processes in the VHDL RTL code that are specifically for assertion statements. Or should the whole assertion stuff be used elsewhere?
Assertions are supported in VHDL at different severity levels (\$\color{red}{\text{Error}}\$, \$\color{blue}{\text{Note}}\$ etc). You may use it to validate different properties/specifications/behaviour of a design. Test benches can be designed around assertions to validate/verify the design.
In VHDL, assert are non-synthesisable constructs, but you may keep it in a synthesisable RTL because they are simply ignored by Synthesisers. In case of Failure severity, the compilation/synthesis stage may itself throw errors before moving to the simulation. Otherwise, these aid during the run-time/simulation.
It's up to the discretion of the designer whether to use assertions in their RTL description.
For e.g: as a designer, you may want to throw warnings if the user is queuing to a full FIFO, or dequeuing from an empty FIFO in the simulation. Or you may want to assert that the data bus width in your design can be configured only in multiples of \$8\$. Or the acknowledgement signal should be asserted in the next clock cycle after the last bit of data was received/sent etc. You can verify these 'checks' by adding a couple of assert statements at the end of your code. It will aid during the simulation via transcripts. It's much better if you can keep them modular/separate for readability.