axi4-stream data FIFO almost full without input

Question

I am very new to FPGA/Vivado.

I am trying to understand how does the IP AXI4-Stream data FIFO work.

To simulate the producer, I connect the tdata and tvalid pin of the FIFO slave interface to all zero. The clock is 100MHz simulation clock. I anticipate that the FIFO will not intake any data since the tvalid is always zero.

However, In the simulation, the FIFO asserted both programmable full and almost full flag and the ready of the slave interface goes down.

Could any help explain what is happening here to me?

Answer 1

A couple of suggestions:

1. Always perform a full reset cycle of any Xilinx AXI peripherals (8-16 clock cycles).
2. Define and drive ALL signals in a testbech, this includes the active-low areset and the t_ready of the M_AXIS interface.