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I'm working on a design that switches 230vAC using mosfets in a back to back configuration (load is approx 2A) The isolated mosfet driver is Si8751.

The top and bottom layers of the PCB will be carrying the current (input/supply on top and output/load on bottom layer). The prepreg between each of the 4 layers is approx 0.2mm thick.

Can I route the driver signal layer (connected to driver and mosfet gate / common source) through the internal layer ? Will the prepreg provide sufficient isolation ? I realise capacitance between the load current and signal could be an issue.

2 Answers2

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I don't know how you plan to lay things out, but whenever I do this (back-to-back MOSFETs with sharing gate nodes and sharing source nodes) I never have to run the gate or source traces under the hot or neutral traces at all. If you do that, then you don't really need to worry about the hot or neutral punching through the PCB layers to the MOSFET gate or source.

If you lay things out properly, you never need to route the gate or source traces over the hot or neutral traces thereby completely avoiding a situation where there is a high potential between the gate or source trace and the hot or neutral through the layers.

"But the MOSFET source sometimes connects to the hot or neutral" you might say. That doesn't really matter. Think about it:

The gate signal is always within 0-20VDC of the source node potential so we'll just treat both of them as being at the same potential for this discussion since the difference is so much smaller than 230VAC.

There's 3 nodes that the 230AC can appear in: hot, neutral, and the source shared by the MOSFETs.

  • When the switch is conducting, the MOSFET source-drain voltage difference is minimal so the difference between gate, source, hot, and neutral are minimal. So no fear of the hot or neutral punching through to the source node while the switch is conducting.
  • When the switch is blocking, one of the MOSFET's connects the common-source node to either hot or neutral through its body diode (based on the polarity of the 230VAC), while the other MOSFET blocks the source node from the other AC line. The largest potential difference appears across the source-drain of the blocking MOSFET.

In both cases, the source node (and by extension the gate node) is always at a fairly similar potential to one of the AC lines so as long as you don't overlap gate or source node traces over hot or neutral traces, there's no high voltage difference to punch through the PCB layers. The only place where a high potential difference is present is between the source-drain of the MOSFETs (the drain being hot or neutral), which you shouldn't need to route over each other as established earlier.

And if for some reason, you somehow were using MOSFETs without a body diode so the source node was floating when the switch was off, it doesn't change the fact that there is still no high voltage difference between two overlapping traces if you laid things out properly.

This seems to have worked fine for me up to 230VAC with transients as high as 1200V (never tried running continuously at 1200V though since I have nothing at work that can produce a 1200V sine wave.)

So I guess my answer is whether or not it will punch through the substrate, you can design things so it isn't really a factor. By the way, sometimes I do have to overlap hot and neutral traces running to an AC-DC converter. And in that case it does seem to hold up but we use 120VAC where I am, not 230VAC. If I have room I'll still separate those layers with the ground trace connected to the ground prong from the wall though.

DKNguyen
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I'd imagine that the lowest voltage of the gate would be 0v, and the highest voltage of AC mains would be 250V under normal operating conditions, transients reaching far above that.

IPC221B says 0.2mm are needed at 250V, which means that if you wanted to follow that specification of creepage and clearance, you'd be right on the line. If if this design is going into a product that will need to pass regulatory I would probably err with caution and put the traces with the largest voltage difference on opposite sides of the board. I'm not sure how the actual ETLs would interpret a requirement like this however AC mains can get above 250 volts with transient events.

Voltage Spike
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  • Isn't the 0.2mm of IPC221B referring to the minimum distance of two conductors on the same internal layer? I don't think it is applicable to determine the minimum distance between two layers since it is not actually a creepage distance. I might be wrong though. – Lars Hankeln Jun 30 '21 at 09:26