4

VHDL generics can have a default value.

The rules for how they are overridden in instantiations and declarations seems to be rather complex, so I wanted to ask about the easiest and safest practices to lower the risk of simulation and synthesis mismatches due to avoidable code bugs or tool issues.

Here is a simple example. What would you do?

Definition:

entity counter is
  generic(
           G_NBITS : integer range 1 to 8 := 3
         );
  ...

Declaration:

architecture behav of counter_tb is

  component counter is

  generic(
           G_NBITS : integer range 1 to 8 := 4
         );

Instantiation:

begin

  counter_inst0 : counter
  
  generic map (
     G_NBITS => 5
    )
Mitu Raj
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P2000
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1 Answers1

5

My thoughts

  1. It's good practice to always mention a default value to generic during entity declaration because it makes sure that the entity can be synthesised and simulated as an individual module if needed.

  2. Whatever default generic in the entity declaration can be overriden during component declaration in a top module*.

  • If there was a default generic in the entity declaration, and you want to use the same value in the top module, you can avoid using generic inside the component declaration.
  • If there was a default generic in the entity declaration, and you want to override it, you may do it so by overriding it inside the component declaration.
  1. In VHDL, generic map gives the final level of overriding. It can override default generic assigned by component and/or entity. Again, this is not mandatory to do generic map, if you want the current default values.

I was never really a fan of component declarations in VHDL cluttering and 'duplicating' on a top module, so I prefer giving a default value to all generic during entity declaration. Then putting all component in a package, or use entity work.entity_name during generic map and port map. And override all generic during generic map () instead, if I want to.

Synthesisability

The rule is that: Simulator/synthesiser should be able to resolve the final value of generic of the instance at any of the three levels mentioned above.

  • The resolved value will be used for simulation as well as synthesis. If it's not able to resolve, it will throw errors during synthesis/simulation.
  • There will be no synthesis-simulation mismatch as the resolved value will be used to synthesise as well as to simulate the instance.

*Top module : is any other module/entity in the higher hierarchy which instantiates the entity in question.

Mitu Raj
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  • Thank you, very good info. There's a lot to unpack here. Q1) to your point 1: do you mean synthesised and simulated with minimal port and generic mapping required to attain a sensible/realistic form of the entity? That makes sense to me. Because as an individual unconnected module it would get optimized away anyway (and so no generics matters), and/or it would not take part in sim. Or is it something else? – P2000 Jun 18 '21 at 16:06
  • And Q2) to your point 3: I agree with the benefits of keeping components in a package, not the top. But what do you mean with "or use entity work.entity_name"? "work" is just the current library being compiled into. So what does this redundancy buy you? – P2000 Jun 18 '21 at 16:08
  • Yea it's the library 'work', if it's the name. No need to include `component` in the top module if the instance is referred like that for mapping. – Mitu Raj Jun 18 '21 at 16:52
  • @MituRaj In item 2), what do you mean by "top module"? Your description could be greatly improved if you used correct terminology rather than jargon. For example, If in the entity you specify a default for the generic value, and a system plans to use that value, then ... – Jim Lewis Jun 19 '21 at 23:01
  • The OP did component declaration. If you want to introduce entity instances, then maybe you ought do it as a separate labeled item so they understand what you are trying to communicate. – Jim Lewis Jun 19 '21 at 23:02
  • Regarding the first query which I didn't understand earlier: No that's not what I meant. You can leave out the default values in the entity X, and if the entity X is part of a system which instantiates it with generic values, the module X will still be synthesised. But if you want to synthesise X separately and simulate, it will not happen because it has no default generics and hence Synthesiser cannot understand your design's hardware complexity. That's why I told it's a good practice to always leave a default value in the entity itself . @P2000 – Mitu Raj Jun 25 '21 at 04:04