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The STM32 G4 reference manual mentions a concept of slow and fast ADC channel.

Quoting from the ADC section of the manual:

Number of external analog input channels per ADC
– Up to 5 fast channels from GPIO pads
– Up to 13 slow channels from GPIO pads

Section 21.4.4 ADC1/2/3/4/5 connectivity identifies for each ADC which channels are slow and fast.

However I have been unable to find any information quantifying the slow vs fast nature of those channels. My concern is about mixing slow and fast channels (as dictated by the available pinout) that are meant to read similar physical quantities in parallel. How much slower are we talking about here? I would like to understand whether that effect could impact my application.

(I am specifically using a STM32 G474RE nucleo board)

StainlessSteelRat
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gg99
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2 Answers2

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The slower channels are multiplexed paths that have a higher input impedance and capacitance (it's a farther length trace), which means the sampling capacitor takes longer to charge. Essentially it's the same ADC that is multiplexed to different inputs. If you go to RM0440 page 610 you'll see this displayed prominently.

Essentially, it's the same speed, but will take longer to get an accurate reading. Note the datasheet for your chip (STM32G474RE) page 142, you'll find table 67 which forms a relationship between the max impedance of the voltage source, and the sample time. For more info on ADCs, refer to AN1636.

Cheers,

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StainlessSteelRat
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Chance K
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Fast = 4Msps Maximum. Slow = 2Msps Maximum. Actual performance depends on external input impedance.

From page 32 of STM32G474xB STM32G474xC STM32G474xE datasheet

4 Msps maximum conversion rate with full resolution

– Down to 41.67 ns sampling time

– Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit resolution)

Fast is a maximum of 4Msps at 12-bit. Decrease resolution and it can be faster. Actual rate depends upon external input impedance \$(R_{AIN}\$ and \$C_{Parasitic})\$.

Table 68. ADC accuracy - limited test conditions

Fast channels@4Msps Slow channels@2Msps

Table shows accuracy for Slow at 2Msps. Again actual rate depends upon external input impedance \$(R_{AIN}\$ and \$C_{Parasitic})\$.

From p153. enter image description here

Page 142 gives \$R_{AIN}\$ for different resolutions. 12-bit being:

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AN2834 - Application note - How to get the best ADC accuracy in STM32 microcontrollers gives more details (and possibly a tool) for fast/slow channels measurements at the same \$R_{AIN}\$ and \$C_{AIN}\$ \$(C_{Parasitic})\$. There may be a problem with this Note since different STM32 microcontrollers have different ADC sampling rates.

Edit

From UM2570 User manual - Description of STM32G4 HAL and low-layer drivers:

On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.

fADC = 60 MHz. So 15 clock cycles @ 60MHz = 4Msps maximum. But 19 @ 60MHz means 3.16Msps, which is significantly different from 2Msps.

StainlessSteelRat
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