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I built a verilogA model for every block used in PLL, I replaced a verilogA model for VCO with a designed one but, I got oscillations imposed on the control voltage as shown below. enter image description here

Fdiv is the frequency of the signal at the output of divider
vc is the control voltage(changes within range of 20mV)
Fout is the frequency of the signal at the output of PLL

Thanks in advance

Mohamed Ossama
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    You got a problem with step noise and no filtering in your filter? No details or specs hmm! – Tony Stewart EE75 Jun 03 '21 at 00:15
  • I use a second order filter to achieve phase margin of 59degrees and settling time of 10uS. For VCO, frequency ranges from 2.35G to 2.45G as the control voltage varies from 0.3V to 0.9V. – Mohamed Ossama Jun 03 '21 at 00:41

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