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Imagine a typical PCB that's small, 6" per side. There's a clocked circuit on it. Making a 1kHz circuit is pretty easy. Making a 2kHz circuit isn't any harder, and neither is a 3kHz circuit. But at some point, this changes, and now the circuit gets flaky. Maybe it becomes an antenna. Maybe a chip is too slow.

Do I just add up the time required by the data sheets for the longest chain-o-logic and add some slack?

Are there any guidelines on when the side effects of a higher clockspeed starts mattering?

Assume that more Hz are better than fewer, of course :-D

Tony Ennis
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    You should probably start with this discussion: https://electronics.stackexchange.com/questions/546355/do-i-need-to-make-a-timing-report-for-min-max-at-static-timing-analysis-in-four/546592#546592 – SteveSh May 30 '21 at 16:49

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Some observations...

  1. The longest chain of logic might not matter unless there is a loop in your data flow. If there is no feedback from data produced by downstream components back upstream then the delay through the circuit might not be an issue.

  2. There are lots of examples of digital circuits built on breadboards working in the low MHz. For instance: Ben Eater's breadboard CPU and this 8-bit cpu with graphics and sound Especially in the second example, there is no special consideration made in regards to layout.

  3. The rise time of signals, not necessarily the clock frequency, is the major determiner of when you have to take into account transmission line effects. That's why the faster logic families (like AC) don't work as well on breadboards compared to HC even at the same clock speed. This SE discussion has a good summary of the suitability of the various logic families for hobbyist work:

https://electronics.stackexchange.com/a/344345/95488

ErikR
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