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A design has a number of simulation ports that should not be tied to FPGA pins.

A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be mapped to FPGA pins.

entity mdl is
  port(
    -- FPGA pins
    clk_i : in  std_logic;
    rst_i : in  std_logic;
    a_i   : in  std_logic;
    z_o   : out std_logic;
    -- Simulation pins only
    sim_only_in  : in  std_logic := '0';
    sim_only_out : out std_logic);
end entity;

The sim_only_* pins can be safely left unused by Quartus, since the inputs have default value.

When running Quartus, the mapper tries to map the sim_only_* ports to unused FPGA pins, which is not desired.

How can I specify that Quartus should just ignore the sim_only_* ports on the VHDL design?

EquipDev
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  • Edit the SDC file, remove all lines that mapped these pins. – Mitu Raj May 20 '21 at 05:56
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    Does this answer your question: [Setting FPGA pins as virtual](https://electronics.stackexchange.com/questions/92185/setting-fpga-pins-as-virtual)? – megasplash May 20 '21 at 08:17
  • @MituRaj: There are no mapping of the simulation pins only, but the problem is that Quartus does a default mapping of unused ports to free FPGA pin. However, the unused simulation ports only should be ignored instead. – EquipDev May 20 '21 at 10:53
  • @megasplash: Thanks, that is the solution :-) If you care to write an answer, I will upvote and select it. Otherwise, I will write an answer myself in a couple of days, so others can have the information available here at StackOverflow. – EquipDev May 20 '21 at 10:54
  • Verilog has compiler directives that are useful for this sort of thing. Using these, you can have 2 sections of code: one of which is used for simulation and one for synthesis. For obvious reasons, you don't want to lean too heavily on this technique. VHDL has pragmas, but I don't have direct experience with VHDL. (`ifdef etc). – Troutdog May 27 '21 at 15:12
  • @Troutdog: VHDL does not have compiler directives like 'ifdef, so text modifications of the source code is not possible, which you appreciate once you have learned to use VHDL properly. However, it then requires handling in the tools for issues like simulation ports; but worst case that could be handled with a wrapper. – EquipDev May 28 '21 at 16:28

1 Answers1

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There is a useful option to use a Virtual Pin assignment. It is often used when compiling a design with a number of pins that exceeds the available physical pin count of a target device. For example, this can be useful to make preliminary estimations for some module, which is only a part of a whole design.

Making a pin virtual can be done via Assignment Editor (Ctrl+Shift+A) like this:

Virtual pin assignment

[Assignment] Specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic element and not to a pin during compilation. The virtual pin is then implemented as a LUT. This option should be specified only for I/O elements that become nodes when imported to the top-level design.

Here is a related video on Using Virtual Pins from Intel FPGA website.

megasplash
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