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It is well documented that N-channel MOSFETs are extremely sensitive to ESD damage. I've personally killed more than one.

Are P-channel MOSFETs just as sensitive? I'm thinking that, since the gate sources electrons rather than sinking them, it wouldn't be, but I don't have the background to confirm that.

The Photon
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user18470
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    Do you mean a *p-channel* MOSFET and an *n-channel* MOSFET? PNP and NPN are types of BJT's, not MOSFETs. – The Photon Jan 30 '13 at 19:43
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    "since the gate sources current" ... MOSFETs are voltage-controlled devices, not current-controlled devices like BJTs. – HikeOnPast Jan 30 '13 at 19:46
  • Dear Pedants, Yes, I mean P-channel and N-channel. Also I mean sources electrons, not sources current. Now please go away and allow someone to answer the question. Jeez... – user18470 Jan 30 '13 at 20:02
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    The point of this website is pedantic -- the whole reason we're here is to teach you and future readers about this topic. It's preferred here if you can edit your question to use the correct terminology; if you don't you're taking your chances that someone else will do it for you. – The Photon Jan 30 '13 at 20:11
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    You'd better lose the attitude if you want a serious answer. But in general, yes, all MOSFETs are sensitive to ESD. If you ever exceed V_gs, even momentarily, you risk permanently puncturing the oxide layer that separates the gate from the channel. – Dave Tweed Jan 30 '13 at 20:11
  • Thank you, Dave. I'd +1 your answer, but it's a reply, not a separate comment. As a followup, is it still the gate lead that's the most ESD sensitive, as it is on the n-channel, or is it the source or drain? – user18470 Jan 30 '13 at 20:20
  • See [Are discrete MOSFETs ESD sensitive?](http://electronics.stackexchange.com/questions/9915/are-discrete-mosfets-esd-sensitive) and also [IR Application Note AN-955 - International Rectifier](http://www.irf.com/technical-info/appnotes/an-955.pdf) – Phil Frost Jan 30 '13 at 21:44

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That's a loaded question-- so here is a loaded answer.

Does it matter? Of course it doesn't. You should be treating all semiconductors with proper ESD handling procedures, and making your designs have the proper ESD protection. It doesn't matter if X is more sensitive than Y-- they are both sensitive, and both require proper handling procedures and proper designs.

Even a device that advertises as having ESD protection, or even something like discrete ESD protection diodes, should be handled as if it were sensitive to ESD.

Remember: ESD does different levels of damage. A part can be damaged by ESD and not show any obvious signs, but then at a later date that damaged part could start failing and you won't know why.

Now, is there a difference in ESD sensitivity between N and P Channel MOSFETs? I have no idea. I do know that there is a huge variation in sensitivity between different MOSFETs of the same channel type. MOSFETs from 20+ years ago are much more sensitive than newer designs. But even that is not a guarantee. I would guess that the variation between MOSFETs of the same channel type is much greater than the variation between N and P channel types.

The point being, I don't think that the difference between P and N channel types is significant, given that there is already a huge variation. And since you should be treating all semiconductor devices with care, it really doesn't matter even more.

  • This doesn't answer my question. Perhaps I misled you with the anecdote in the first paragraph. The reason for asking is to determine if a clamping diode makes sense in the design, not to determine if I can shuffle around on carpets with them. Thanks anyways; lectures are always a blast. – user18470 Jan 30 '13 at 20:37
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    @user18470 If you can exceed the voltage rating of the part, then you need protection. It is as simple as that. It doesn't matter if you exceed it due to ESD, or from inductive kickback, or whatever. –  Jan 30 '13 at 20:55
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Are P-channel MOSFETs just as sensitive? I'm thinking that, since the gate sources electrons rather than sinking them, it wouldn't be

A key point worth mentioning is that ESD voltages come in both polarities, positive and negative. So the normal function of the device (whether current is normally going "in" or "out" of the device) isn't really a factor. The ESD could come along with whichever polarity is more "unusual" for any particular device.

The Photon
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  • Good point. I believe it's the gate that needs the most protection on an N-channel MOSFET. For example, I've seen references to protecting it with a zener diode. Is that true for P-channel as well then, but with the zener in the opposite direction? Or is it the source or drain on a P-channel that becomes the most sensitive to ESD? – user18470 Jan 30 '13 at 20:34
  • +1 for a concise and professional answer to someone that said "Now please go away and allow someone to answer the question. Jeez..." – HikeOnPast Jan 30 '13 at 20:35
  • @user18470, in either case, the damage comes from breakdown of the gate oxide. So a + or - gate voltage relative to either source or drain is a problem. But where you put your protection device depends on which terminals are exposed to discharges. If someone applies +500 V to the drain it's just as bad as -500 to the gate. But usually gates are more likely to be connected to input wires of your circuit. – The Photon Jan 30 '13 at 21:17
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An EOS (Electrical Over Stress - of which ESD is one part) event damages a device by imposing an electric field that is too high for the device. That in itself may be sufficient to damage the part, but once current starts to flow from the device breaking down, heating then become the dominant effect. GOX (Gate OXide) is the most sensitive aspect of a MOS type transistor but S/D's and various junctions can all be damaged, as well as contacts, wiring and interconnect. If it cannot support the current.

If PMOS and NMOS are made in the same process (mainly the GOX being the same thickness) then there is no difference between in the native sensitivity of the Gate to EOS in processes less than 0.35u. However, because of the mobility differences PMOS transistors tend to be 2.5 X larger that NMOS devices to match the transconductance of the devices. In some cases this may help protect against an ESD event as the capacitance is also 2.5X higher and for a fixed charge transfer the generated voltage will be 40% and thus the E-Field will be 40%. However, there are process specific reasons why having a larger gate area might also hurt the PMOS.

EOS can damage the device without any noticeable/visible effect on the device if it causes a shift in operating conditions. Like if the GOX is compromised but not fully ruptured.

In CMOS devices the GOX breakdown is principally what limits a given process voltage of operation and this scales (mostly) linearly with GOX thickness. So a finer process, means thinner GOX means lower voltage. So a 90 nm process might have 2 nm thick GOX and an operating voltage of 1.1 V. Which is an E-field of 500 MV/m and only the equivalent of 12 bond lengths - approx - it is amorphous. I that same process the threshold voltage could be in the range of 300 mV to 500 mV.

If you are talking discreet devices, you have no way of knowing if the processes are comparable, even from the same manufacturer.

ESD is a complex subject with many variables in the process and many failure mechanisms.

As the other answers have suggested, treat everything as ESD sensitive.

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