Question on timing diagram of a SR Latch with different gate delays

Question

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, #5)

module rs_latch(
   input S,
   input R,
   output Q,
     output Q_L
        );
    
    assign #10 Q_L = ~(S | Q);
    assign #5 Q = ~(R | Q_L);
    
endmodule

I expected Q and Q_L would oscillate right after 500ns, when both S and R are changed to 0. When the gate delays were the same #5, they did oscillate. However, in this case, as you can see from the image below, it is not oscillating.

Below is a hand-drawn diagram that I had expected to appear.

Could you please explain why it is not oscillating?

dave_59 · Accepted Answer · 2021-05-19T07:05:25.887

The problem is caused by what is known as the Inertial Delay Model used by HDLs like Verilog and VHDL. The output of a continuous assignment or primitive gate cannot change faster than its propagation delay. Another way to think of this is an output can only have one scheduled change pending at any point in time.

At simulation time 500, Q gets scheduled to go to 1 at time 505, and Q_L gets scheduled to go to 1 at time 510. Then at time 505, Q goes to 1 as scheduled. Because of the change to Q, the continuous assignment to Q_L gets another evaluation at time 505 to go back to its current value, and the previously scheduled assignment to 1 at time 510 gets cancelled. Now there is nothing scheduled until R or S changes again.

In contrast, the Transport Delay Model allows the output to change as fast as the inputs, regardless of the propagation delay. It can queue up as many pending changes as needed. Module path delays in a specify block, and non-blocking assignments use transport delay models.

I truly appreciate your answer. So it depends on how you write the code, am I correct? How about in the real-world situation? If I realize a SR latch with two NOR gates with different gate delays, will `Q` oscillate? — shinhong, May 19 '21 at 14:51
In the real-world, most synthesis tools will not allow you to model a latch with combinatorial feedback and SR inputs will never change both instantaneously and simultaneously. All signals are analog and you have look at timing windows for what is called [metastability](http://www.asic-world.com/tidbits/metastablity.html). — dave_59, May 19 '21 at 15:31

Question on timing diagram of a SR Latch with different gate delays

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