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I have a signal that starts at 0 V and linearly increases to 2.4 V as output and I would like to buffer it such that it cannot be influenced by resistive loads. The issue is that the only buffer circuit I've learned is the source follower (common drain amplifier) such that it takes as input (gate voltage) the output of my previous circuit. But as this signal starts at 0 V, the gate voltage is not high enough compared to the threshold voltage and then the transistor is not in saturation and the circuit does not work correctly.

As you can see on this simulation, there is a delay before it starts following (also the slopes are not the same).

enter image description here

And here is my source follower with L=350nm and W = 1000nm.

enter image description here

How can I solve my issue, either by another buffer circuit for resistive load or by having a trick so that the source follower can work for input lower than Vth?

Null
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Saens
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  • There are definitely techniques to achieve this (the same ones used for the output stages of rail to rail op amps) but we need a bit more info about your problem constraints and requirements. This looks like it's an open loop circuit -- are there any reasons that would preclude you from using a high gain stage and a feedback network to make the closed loop gain unity? – nanofarad May 16 '21 at 14:31
  • Notice that the "C" in CMOS stands for complementary. It means, that you have complementary nMOS and pMOS FETs at the output to drive either high or low. This is not what you have in your circuit, so I changed the tag from CMOS to MOSFET. – jusaca May 16 '21 at 14:35
  • @nanofarad I also though of using a OPA as follower but I wanna keep thing simple. I'm doing it only on the simulation tool so I don't have any constraints – Saens May 16 '21 at 14:51

2 Answers2

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Try the following circuit. Note that M1 will only be "on" if the Vgate is Vsig + Vth. That will give you an extra voltage to drive the main transistor. enter image description here

user3795717
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You cannot design anything without full specs.

In this case R load and load regulation tolerance X%, voltage linearity error, BW, gain error, offset error, temp range. Vdd tolerance. Etc.

From this you choose RdsOn at some power % of load R and use complementary high gain buffered inverters (3 stages) then R ratio of 1:1 as an inverting amp like that done for 4000 series CMOS. Excess gain lowers Zo, phase margin needs integration.

Otherwise the obvious solution is an OP Amp that does what you want or with complementary emitter followers with negative feedback and excess Vcc to increase headroom.

You are defining a problem called load regulation error which is just due to R ratio’s or active current limiting.

Tony Stewart EE75
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    I don't have specs. I just want to buffer my output in a reasonable way. I also though about using OP Amp as follower but I wanna keep things simple and do it with only a few component. – Saens May 16 '21 at 14:54
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    @Saens, at the very least you must specify what's the lowest value resistor you want to be able to drive. Driving a 1000 ohm resistive load is much easier than driving a 0.001 ohm resistive load. – The Photon May 16 '21 at 14:55
  • it's more like 10k resistive load – Saens May 16 '21 at 14:57
  • 10k makes is easy with a 4000 series buffer and 10k input , 10k feedback to drive down to 300 Ohms easily. Cascade two for non inverting with offset R added – Tony Stewart EE75 May 16 '21 at 15:00
  • Here’s an unbuffered custom solution, that almost works. https://tinyurl.com/ygxwh78s – Tony Stewart EE75 May 16 '21 at 15:41