How to change status of pin in Spartan 3E FPGA

Question

Verilog Code:

`timescale 1ns / 1ps

module blink (customClk, LED, statusPIN);

input customClk;
output statusPIN;
output LED;

reg [31:0] counter;
reg LED_status;

initial begin
counter <= 32'b0;
LED_status <= 1'b0;
end

always @ (posedge customClk) 
begin
counter <= counter + 1'b1;
if (counter > 5000)
begin
LED_status <= !LED_status;
counter <= 32'b0;
end


end

assign LED = LED_status;
assign statusPIN = LED_status;

endmodule

UCF File:

NET "LED" LOC = F12;
NET "LED" IOSTANDARD = LVCMOS33;
NET "statusPIN" LOC = E8;
NET "statusPIN" IOSTANDARD = LVTTL;

Testbench code:

module main_tb;

    // Inputs
    reg customClk;

    // Outputs
    wire LED;
    wire statusPIN;

    // Instantiate the Unit Under Test (UUT)
    blink uut (
        .customClk(customClk), 
        .LED(LED), 
        .statusPIN(statusPIN)
    );

    initial begin
        // Initialize Inputs
        customClk = 0;
        
        // Add stimulus here

    end
    always #10 customClk = ~customClk;
      
endmodule

LED is blinking too fast but when I read the status of the pin, it is still low. Where is the problem in code.

Thank you for your time.

A "counter" is a synchronous circuit. It has clock. You don't have clock in your design. — Mitu Raj, May 15 '21 at 12:14
I added the testbench but in simulation, customClk is always high — Dipnarayan Das, May 19 '21 at 08:17
If LED is blinking fast, you should figure out what's the source clock frequency and to which frequency, your 5000-counter is dividing it down. — Mitu Raj, May 19 '21 at 08:33

score 1 · Answer 1 · answered May 15 '21 at 12:13

1

You need to use an

always @(posedge clk)

block. "always @(*)" is only for combinatorial logic but you have to build synchronous logic to make a counter. With "posedge" your always-block only gets triggered once per clock cycle.

answered May 15 '21 at 12:13

Jonathan S.

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I added the testbench but in simulation, customClk is always high – Dipnarayan Das May 19 '21 at 08:17

How to change status of pin in Spartan 3E FPGA

1 Answers1