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I have a falling edge detector built based on a D flip-flop as shown in the following figure:

circuit

Components: 74hc74, 74ls04n, 74hc08

A sample output is shown below (I invert the output since I need it as an active low):

logic analyzer output

My question is why it sometimes doesn't detect the falling edge?

Thank you all so much!

The problem was the logic analyzer sampling rate and frequency as @Elliot Alderson mentioned.

I re-configured the PulseView and finally could capture the output correctly (indeed there was nothing wrong with the circuit itself)

logic analyzer output

SamGibson
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Sina
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    How did you get the output waveforms? Is this a simulation or a real circuit? If a real circuit, how did you capture the signals? – Elliot Alderson Apr 08 '21 at 16:29
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    This circuit is twitchy and is relying on propogation delays... –  Apr 08 '21 at 16:49
  • Have you verified that with an oscilloscope? Maybe that is ground bounce? Or are you really driving a CMOS input directly with a TTL output, without a pull-up resistor? – Justme Apr 08 '21 at 17:04
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    Thank you all for your comments. @ElliotAlderson This is a real circuit and I captured the output with a logic analyzer. – Sina Apr 08 '21 at 18:06
  • @JonRB any solution to fix it? – Sina Apr 08 '21 at 18:09
  • @Justme I just checked it with logic analyzer – Sina Apr 08 '21 at 18:09
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    This is just block diagram you have shown. We never know if this is what you ACTUALLY wired and built on hardware. – Mitu Raj Apr 08 '21 at 18:22
  • This circuit does work in theory. If you have built this in real hardware and it not working as expected, there must be a mistake / glitch somewhere. Show an image of your circuit and your results. – David777 Apr 08 '21 at 18:28
  • Put a 1kohm resistor from the 74LS04 output to 5V supply voltage. Does it help? – Justme Apr 08 '21 at 18:48
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    Would you need a synch flip flop chain preceding this like you would in an FPGA to handle metastability? – DKNguyen Apr 08 '21 at 19:50
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    @JonRB Is it? Remove the flip-flop and it becomes the circuit you're probably thinking of. With the flip-flop, it looks perfectly cromulent to me. Provided the data doesn't change exactly on the clock's rising edge. – user253751 Apr 09 '21 at 11:57

1 Answers1

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My guess is that the pulses are too short for the logic analyzer to catch them. Logic analyzers sample the signals at a constant rate, and if the time between samples is longer than your pulse width then the logic analyzer simply won't see it.

Try decreasing the sampling time significantly, or switch to an oscilloscope.

Elliot Alderson
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