Why does Camera Serial Interface (CSI-2) have multiple data lanes?

Question

I have been reading through the CSI-2 spec and some controller documentation and I see that it has up to 4 data lanes. If data is transferred on 4 lines at a time then how is it a serial interface anymore? Isn't it a parallel interface now? And how is it different from Camera Parallel Interface?

Answer 1

In a parallel bus, each bit of a single data unit is passed on a separate wire and all wires change (source) simultaneously and are taken (destination) simultaneously.

Parallel data transfer happens under control of separate handshaking wires, such as a sync clock with data valid(s), an async write strobe, an async read enable and so on.

Example data units are bytes (8 bits) and dwords (32 bits). 'Simultaneously' means within some defined timing limits.

In a serial interface, each bit of a single data unit is passed on a single wire one after the other.

The serial data unit is modified before transmission, just for the trip across the wires so the receiver can identify the data. The serial receiver will later modify the data back to the original. Examples are UART START/STOP/idle bits, PCIe v1.0 8b/10b encoding, 128b/132b.

In a multi-lane serial interface, each lane is carrying its own data units with its own timing. The data units are received and checked independently then recombined into a single, faster data stream. If fewer lanes are available the link works, just slower.

This is simplistic and general and there's more subtleties and variants in all this. But it gives you some definitions and differences.

Answer 2

No, a serial interface with multiple serial lanes in parallel does not make the whole thing a parallel link, it is still a serial link.

And there are multiple lanes in a link because the data rate is too high to fit into a single lane.

Answer 3

CSI-2 is a scaleable bit-multiplexed interface. It’s a descendant of LVDS, which uses a fairly simple parallel-to-serial scheme to reduce pin count. CSI-2 also has a low-power parallel mode that remaps the differential pairs to a byte-parallel interface. This mode still gets used a a way to achieve line sync even when high-speed mode is in use.

Yes, CSI-2 is a bit of a hot mess, mixing LVDS and single-ended. It’s a pain to design.

To make matters worse, in high-speed mode CSI-2 uses a separate bit clock, the channel coding isn’t made DC-free, and the drive strength is kind of weak. This limits CSI-2 to short, ‘inside the box’ interconnections. Which is perfectly fine for its mission, to be a low power, low silicon, modest pin count connection for sensors.

As camera applications have grown in industrial and automotive, this ‘in the box’ limitation has led to several true SERDES standards that bridge CSI to a single coax cable. These include GMSL, FPD-Link, THine V-by-one and several others (including an automotive proposal from MIPI themselves called A-PHY.) They all adopt DC-free channel coding along with embedded clock timing, similar to techniques used in PCI Express, SATA, DisplayPort and other serial standards.