In addition to the OTF (other fine answer), slew rate is directly related to the half power bandwidth or -3dB of the DSO and the current limiting of the Op Amp into a capacitive load when measured from 10 to 90% of the step voltage.
Most Op Amps (OA) have active current limiting unlike logic drivers, so the slew rate converted to large signal BW is always much lower than the BW.
In order to standardize slew rate specifications the OEM (original equipment Mfg.) will specify the conditions for the test result.
Let’s take an example of a high slew rate (GP) general purpose OA (not current feedback which are much faster)
If they do not give a load capacitance for slew rate test on high BW, assume it is the fastest active Diff. FET probes you can get, (TEK) much faster than the D.U.T. (Device under test)
LM7171 G.P. Fast buffered Op Amp.
- all limits are specified for V+ = +15V, V− = −15V, VCM = 0V, and RL = 1 kΩ (25’C)
- (3) Slew Rate is the average of the raising[rising] and falling slew rates.
SR Slew Rate (3)
PARAMETER CONDITIONS
Av =+2,Vin =13Vpp 4100 V/μs (Vo=26V)
Av =+2,Vin =10Vpp 3100 V/μs (Vo=20V)
The implied rise time is thus for 4100[V/s] for 80% of 26V=20.8V is now ~ 5 ns (even if datasheets capitalize seconds, S=Siemens, lower-case “s” is the correct abbr.)
The equation for slew rate to rise time Tr is a follows
$$f_{-3dB}=0.35/t_R$$ the rise time from 10 to 90% is thus 20.8 V/4100 μs ~ 5 ns or \$f_{-3dB}=70 MHz\$ for large swing and the datasheet indicates Av=2 small signal BW=215 MHz @ +/-15V supply @ 25’C
This is a special buffered OA with push/pull limit of 100/100mA into a 100 ohm load (min).
So could this be measured on your DSO with f-3dB=30 MHz and 100 MS/s ?
No, but you can measure 0.35 / 30 MHz = 11.67 ns as the fastest risetime for a faster device.
So this is how you measure risetime.
Tolerances depend on if you use identical assumptions in the datasheet with measurement tolerances of your NIST-traceable calibrated DSO. Thus includes neglible probe capacitance or as you estimate from dV/dt=I/C. (100mA/1pF=100 kV/μs) so a 100kV/4.1kV=+24pF so a load less than half this much, might be possible to be used here, such that the slew rate of the probe does not impact as much on the D.U.T. (I leave the error calculations to you.)
In this case the internal capacitance on the OA and PCB is the limiting factor.
So there is much more to doing a tolerance analysis than just reading the datasheets! Right @Andyaka ?