Verilog testbench for inout

Question

Can anybody please help me out with how to write test benches for inout ports in Verilog? I can't instantiate them as reg type variables in the test bench.

Answer 1

You can't drive an inout directly as a reg. inout types need to be wire. So, you need a workaround.

The workaround is creating a driver pin that shares the same wire as the module signal. To do this, define a reg variable for your 3-state test signal, then assign it to the inout pin to connect it.

As follows:

module my_testbench;

wire inout_pin;   // bidirectional signal from DUT
reg inout_drive;  // locally driven value
wire inout_recv;  // locally received value (optional, but models typical pad)

assign inout_pin = inout_drive;
assign inout_recv = inout_pin;

then later in your testbench, you can manipulate the drive state of the tristate pin:

initial begin

inout_drive = 1'bz;    // default high-Z

later....

inout_drive = 1'b0;    // drive a value, propagates onto inout_pin

As you expect, the inout_pin will assume the value you drive it with inout_drive as long as the DUT signal is in high-Z state. Likewise, inout_recv will follow the value driven onto inout_pin.

Strictly speaking, you don't need inout_recv to use the value present on inout_pin in your test bench, but it reflects modeling a tristate I/O pin connected to the DUT.

Answer 2

You can test them the same way as you assign them from within the module:

reg dir;
reg gen;
wire bidir;

assign bidir = dir ? gen : 1'bz;

MyAmazingModule DUT (
    .myInOut(bidir)
);

initial begin
   dir = 0;
   gen = 0;
   ...
end