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So this is what I understood from what my professor said, but I don't think it's the right answer. What am I doing wrong? I'm sure It's just some small thing that I'm getting mixed up.

Given instruction: SW x8, -6(x4)

What I thought it meant: Take the content of source register x8 and subtract 6 from it. The result gives the memory address. Now, store the content of register x4 into the obtained memory address.

RhinoECE
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    I’m voting to close this question because this is actually about the assembler code, not the electrical engineering behind CPUs. This is, in the best and positive sense, a candidate for Stackoverflow.com, not electronics.stackexchange.com . – Marcus Müller Mar 23 '21 at 23:21
  • How can you read the description of this instruction that way??? Can you provide a link to the documentation you are reading? Or a link to the textbook? The ones I have are very clear and very easy to understand. And your writing doesn't look much like it. – jonk Mar 24 '21 at 04:04
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    @MarcusMüller Computer Architecture, ISA related, processor assembly code questions, they have always been welcome and well answered by EESE community over the years. – Mitu Raj Mar 29 '21 at 15:40

1 Answers1

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With RISC-V assembler, the operand order is destination/source except for stores.

Thus, your example instruction reads:

       
SW x8, -6(x4)
   ^     ^
   |     |
   |   destination
   source

The store word (sw) instruction reads the lower 4 bytes of your source register and stores them into memory at the address given in the destination operand.

In your example, -6(x4) is the usual assembler syntax for specifying a register where an address is stored (x4) and a constant offset (-6) to that address.

In prose your example instruction reads:

Store the lower 4 bytes located in register x8 into memory at the address obtained by subtracting 6 from the address that is located in register x4.

More formally:

sw src, off(dst) => M[dst + off] = src[31:0]

See also for example Annex A RISC-V Instruction Listings, page 162 of The RISC-V Reader by Patterson and Waterman, 2017.

maxschlepzig
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