Configuring the unused pin in CPU

Question

I have just started designing the embedded systems. While designing the CPU and thinking from the reliability point of view I actually had few curiosities

1. For the unused pins which are tied up to Vcc using a pull up resistor - Lets say there is and fault and we have two conditions a) that is in floating state b) if its short then tied directly to Vcc. I would like to know the effect of both this conditions on the working of CPU and system?

2. Similarly for the unused pins which are tied up to GND using a pull down resistor - Lets say there is and fault and we have two conditions a) that is in floating state b) if its short then tied directly to GND. I would like to know the effect of both this conditions on the working of CPU and system?

I am using SM320F28335PTPMEP microcontroller for my purpose.

Answer 1

I think your cases 1a and 2a are the same thing.

If the pin is configured as an input, then shorting it to either Vcc or GND is pretty harmless. If it's left floating, then you will get an indeterminate result in reading the pin. The pin will be vulnerable to ESD (electrostatic discharge), but that's unlikely to matter so long as the board isn't touched.

If the pin is configured as an output, leaving it floating is harmless. Forcing it to either Vcc or GND could damage the microprocessor.

Of course, if your board is so poorly made that the pull-up or pull-down resistors are either missing or shorted out, then you probably have much bigger problems to worry about.

Answer 2

There is no universally correct answer to your question in the way that it's written.

Think about the likelyhood of a single fault occuring, and the risk involved should that fault occur. The effect of this really depends on what your system does.

E.g. a pin shorting to ground might have no effect or it could cause a plane to loose control and crash.

A common way to do this is risk analysis.

You might also perform an FMEA

I you were really worried about faults, then make your unused pins inputs with external weak pullups and then check their state in software to detect the fault condition.

But that might not detect all possible faults and if such a fault should occur it could perhaps just as easily effect a more critical component such as the power supply, taking out more than just one pin.

However if you were to do this I would call into question your packaging, why did the fault happen in the first place and what could have been done to prevent it?

Answer 3

In most common scenarios, if you can't trust your software not to flip random GPIO pins, then you've got bigger problems already. So, it's not unreasonable to assume that any GPIO pin set as an output will remain at whatever state you set it to, barring software bugs. There are ways of detecting such bugs at runtime and recovering, but it's quite application-specific and it's best not to reinvent the wheel. If you don't have any specific legally mandated requirements that apply to your device in that respect, an appliance safety standard such as IEC/UL 60730 provides plenty of time-tested approaches in that area. This Zilog app note covers firmware design for an IEC 60370 Class B application - the Class B approach is a reasonable trade-off when no stricter requirements would be dictated by engineering analysis.

So the next thing you can do is divide all the unused pins into two groups of roughly equal number of pins. Ideally just alternate them between the groups in physical pin order. Then connect group 1 to 0V, and group 2 to VCCIO (whatever it happens to be on your MCU). And the outputs exactly to the logic states you hard-wired them to, and configure them as outputs.

This reduces the effective impedance of the I/O supply busses within the MCU itself, and is usually beneficial for electromagnetic compatibility and signal integrity. Less ground bounce within the MCU means better noise rejection on inputs, and it also means that the output signals have less noise on them.

See this answer for more details.