Unable to simulate a JK Flip-Flop using VHDL dataflow modelling

Question

I want to write code and simulate waveforms for flip flops strictly using dataflow modelling. In this case I'm simulating a jk flip flop with only j,k and clock (no set , reset). It compiles fine, but when I try to simulate run the waveforms (j,k,clk,q,qbar), my modelsim stops responding. I guess it has something to do with using output as input, as I'm not well versed with sequential circuits in vhdl but combinational circuits seem doable.

library ieee;
use ieee.std_logic_1164.all;
entity jkff_data is
   port (clk,j,k : in std_logic;
            q,qbar : out std_logic);
 end jkff_data;
architecture dataflow of jkff_data is
signal s1, s2, s3, s4 : std_logic;
begin
   s1 <= not(j and clk and qbar); 
   s2 <= not(k and clk and q); 
   s3 <= s1 nand qbar; 
   s4 <= s2 nand q; 
   q <= s3 ;
   qbar <= s4 ;
end dataflow;

my circuit with signals

Can you try q and qbar outputs as buffer type port instead of out type. — Berker Işık, Feb 25 '21 at 08:42
You have a combinational feedback loop. Synthisers will flag it as DRC error and you won't able to use this "unpredictable" logic on an actual board. Not sure what you are trying to achieve with this code. And of course if it's for simulation purpose only, then you have infinitely triggered concurrent statements. — Mitu Raj, Feb 25 '21 at 12:17
Feedback with negation and zero delays means you get delta cycle oscillations where each delta cycle causes another until you hit the iteration limit. Some FPGA synthesis tools won't balk when synthesizing feedback loops. Preventing oscillation requires tuning delays or using a pulse derived from a clock edge. Alternatively you can use a master-slave flip flop. — , Feb 25 '21 at 23:07
It's not for FPGA or anything. I want to simulate jk ff using dataflow modelling, without using testbench (just adding all signals to waveforms and checking if it follows the truth table) — Ayush Sinha, Mar 03 '21 at 06:18
@AyushSinha Hey, addressing the question, which is about the Modelsim freezing. I tried to reproduce it as you intended, without a tesbench by changing inputs of your jkff_data in the waveform, but it looks to successfully simulate for me. It gives undesired unknown values at the outputs, but it is another question, I guess. So could you give some more details, what leads to Modelsim freezing (software version, compilation options, etc.)? Moreover, is it still a problem? — megasplash, Mar 03 '21 at 09:09
@megasplash , Did you use the exact same code that is in my original post? What I do is I start it's simulation then add all the signals to the waveform. Then I clock the clk variable and start forcing j,k to diff values to get o/p as q and qbar. What is your process of forcing, clocking without testbench? — Ayush Sinha, Mar 03 '21 at 14:07
This is not the circuit of JK F/F. This is JK Latch's circuit. In popular naming convention, F/F are classified as edge triggered and Latches as level triggered. This is a level triggered latch. — Mitu Raj, Mar 03 '21 at 15:13
@AyushSinha Yes, exactly that. You write in a comment to the answer, that simulation gives you the results. So do you still have a problem of freezing Modelsim? — megasplash, Mar 03 '21 at 15:52

Shashank V M · Accepted Answer · 2021-03-03T13:11:26.240

Note: The circuit you are using is not the correct one. See JK latch, possible Ben Eater error?

The output remains unknown when simulated without a reset. Try this one which uses a reset:

Try this code:

use IEEE.std_logic_1164.all;

entity JK_FF is
port (J, K, CLK, reset: in std_logic; -- inputs
      Q, Q_bar: out std_logic);
end entity JK_FF;

architecture dataflow of jk_ff is
signal s1, s2, s3, s4 : std_logic;
begin
   s1 <= not(j and clk and q_bar); 
   s2 <= not(k and clk and q); 
   s3 <= s1 nand q_bar; 
   s4 <= s2 nand q; 
   q <= s3 and (not(reset)) ;
   q_bar <= s4 and reset;
end dataflow;

You can simulate it on EDA Playground (requires logging in) in your browser here: https://edaplayground.com/x/wDX5

The problem is you can't set an initial value for Q and Q_bar without a reset. This code uses an asynchronous reset, but you should use a synchronous reset if you are targeting an FPGA.

Of course, the synthesizability of this is another question. The synthesizability of this VHDL code depends entirely on the synthesizer you are using. An HDL code might work in simulation but may not necessarily be synthesizable.

For ASICs a reset signal is recommended for all flip-flops except pipeline registers.

See also:

If you want a JK Flip-Flop in VHDL that works, use this:

library IEEE;
use IEEE.std_logic_1164.all;

entity JK_FF is
port (J, K, CLK: in std_logic; -- inputs
      Q, Q_bar: out std_logic);
end entity JK_FF;

architecture behaviour of JK_FF is 
signal QINT:std_logic;
begin
process (CLK) 
  variable JK : std_logic_vector( 1 downto 0);
  begin
  JK := J & K; 
  if rising_edge(clk) then    
   case (JK) is
      when "00" => QINT <= QINT;
      when "01" => QINT <= '0';
      when "10" => QINT <= '1';
      when "11" => QINT <= not QINT;
      when others => QINT <= 'X';
    end case;  
  end if;
end process;
Q <= QINT;
Q_bar <= not QINT;
end behaviour;

If I try plotting signals by adding to wave, it doesn't give the right outputs. For eg. I start with reset = 1, clk is a clock, it gives q = 0 (fine). I force reset to zero, and J = 1, K = 1. Q should be toggling but it doesnt and stays stuck at Q=0. — Ayush Sinha, Mar 03 '21 at 07:45
@AyushSinha When you have not built a JK FF, how can you expect a JK FF simulation results? — Shashank V M, Mar 03 '21 at 09:50
I have done jk ff using behavioural modelling already, I need to do it using dataflow strictly. And my first comment was regarding the case when I simulated the code that you first provided (the non behavioural one) — Ayush Sinha, Mar 03 '21 at 13:54
@AyushSinha that is not a jk ff. The first one is a jk latch with a reset — Shashank V M, Mar 03 '21 at 13:56
So In general dataflow and structural styles aren't good for building sequential circuits. As for the initial state of Q, You used reset. — Ayush Sinha, Mar 05 '21 at 17:34
I simulated and got this. It is a latch(level triggered) as one user pointed out. https://ibb.co/WKMzFNh But at some points it doesn't seem to give correct outputs, like j = 0, k = 1 and q = 1. Is it expected? — Ayush Sinha, Mar 05 '21 at 17:49
@AyushSinha build a level triggered latch using behavioural modelling and then see if its outputs match what you are building — Shashank V M, Mar 07 '21 at 15:19

Unable to simulate a JK Flip-Flop using VHDL dataflow modelling

1 Answers1