HSPICE create a voltage source in top level and instantiate it in a .subckt

Question

I am fairly new to HSPICE and I am investigating someone else's testbench and I am trying to track down where is the vsource generator used in the .lstb analysis in this testbench.

I am a bit shorthanded in providing a bigger picture of the problem, but I was hoping just clarifying the used syntax would help me out a lot actually.

So, to narrow it down, I am curious to find the net location where stability analysis was performed. In the whole testbench file there is only one .lstb call-up, luckily, and there is also only one VV0 mentioned in the file.

VV0 imirrsrc[1] vss dc='p_vload'

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.lstb mode=single vsource=XREFGEN.XLOOPBRK.vv0

'p_vload' is undefined throughout the testbench file.

Judging from the way vsource was defined in .lstb it means vv0 is instantiated inside the XLOOPBRK? That is the way to interpret the syntax XREFGEN.XLOOPBRK.vv0 ?

If that is the correct case, I am unsure of how it is declared in the first line then just as VV0 imirrsrc[1] vss dc='p_vload'? Is this doable?

Or is the correct syntax:

.param p_vload=someValue $assuming p_vload is desired to be defined
XREFGEN.XLOOPBRK.VV0 imirrsrc[1] vss dc='p_vload'

.lstb mode=single vsource=XREFGEN.XLOOPBRK.vv0

I know reading through someone else's work is always cumbersome, but I need help to sort my thoughts on this one...Am I reading into this correctly?

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EDIT: I am not sure if I should delete the original text, but here's what I wanted to add so far:

I made my testcases to confirm my rights and wrongs here and I couldn't replicate my question, so my current answer is: NO you can't create a voltage source this way and use it in a subcircuit moreover, you are probably seeing incomplete stuff, and you need the p_vload defined at some point.

It made me realize my question is not good enough.

So, can you create a voltage source in your testbench/toplevel, and then instantiate it (wire it) in a subcircuit right there in your toplevel testbench?

I couldn't do it in my testcases (it failed), but maybe I am missing some syntax knowledge again. So, is something like this possible:

# toplevel testbench, assuming nodes in MySubckt2 are 2 and 0
xMySubckt.xMySubckt2.V1 2 0 dc=5V

.dc xMySubckt.xMySubckt2.V1 0 5 0.25

Answer 1

I realize I've made a mistake, my apologies. I meant it backwards, so I'll rewrite the answer. Feel free to downvote.

I still don't understand exactly what your requrements are, so I'll just present the two versions of what I perceive to be the possible answers. Take your pick, or let me know if none of these answer your question.

In short: parameters defined in the top level schematic can be accessed inside the subcircuits through .param statements inside the subcircuit. SPICE netlist example:

.param p_vload=2
V1 in 0 {p_vload}
XU1 in out test x={p_vload}
.subckt 1 2 test params: x=3
B1 2 0 V=V(1)*x
.ends test

V1 is in the top level schematic, connected between nodes in and ground. It has the {p_vload} value, which is a .param defined also in the top level schematic. XU1 is an instance of the subcircuit test, connected between the nodes in and out. The subcircuit is made of a behavioural source, B1, which takes the voltage at pin 1 and outputs it at pin 2, multiplied by a constant, defined as a .param. This parameter, x, is only available inside the subcircuit, not outside, but it can be assigned a value from the top level schematic: the XU1 instance has x={p_vload}.

This is, partly, what I meant with my comment: the .subckt line can omit the params: line, and then x would be undefined inside the subcircuit. Attempting to use the subcircuit will fail, unless an explicit instantiation of the test subcircuit is done such that x is defined (the x={p_vload} part).

This was the case for an external parameter accessed inside a subcircuit. The reverse is not possible, unless the parameter is used as a voltage or current, and referenced through an additional pin in the subcircuit. Netlist with an extra pin:

.param p_vload=1
V1 in 0 {p_vload}
XU1 in out in test
.subckt 1 2 EXTRA_PIN test
B1 2 0 V=V(1)*V(EXTRA_PIN)
.ends test

The third pin, EXTRA_PIN, in this case can be used such that V1 can be connected to it and B1 can take that voltage, V(EXTRA_PIN), and do something with it. Note that EXTRA_PIN can only provide a voltage (or current), not a parameter. All .params are evaluated prior to simulation start. Also, just adding the EXTRA_PIN is not enough, the subcircuit must be modified in order to be able to use it: B1 has *V(EXRA_PIN) instead of *x.