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We've been using a quad RS485 setup for some time. No problems.

Now we'd like to increase the speed over what we can get away with on RS485 with the micro we're using. Essentially, we've been implementing an SPI port using four RS485 parts.

I've started wondering about using an Ethernet PHY and transformer as a physical layer and sort of "bit-banging" the MII interface to it. Is this a common technique, or am I missing something critical?

Goals: keep the differential benefits, better isolation, increase speed considerably.

Distance would never be greater than 10 meters.

Thanks in advance!

GaryLa
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  • hm. You'd definitely want to go for the reduced complexity version of MII (RMII), I guess. How much resources does your microcontroller have to spare? I feel that if you need more speed than RS485 can do over 10m, then you really have relatively beefy on hand and could actually do Ethernet, with all the practical benefits of doing so. – Marcus Müller Feb 08 '21 at 23:53
  • All this micro does is sample some inputs and drive them out the RS485. Likewise, it receives samples and drives them locally to outputs. – GaryLa Feb 08 '21 at 23:59
  • yeah, so how much resources does it have left after doing that? WHat rates are we talking here? What kind of MCU? Note that either way, you'll need to be able to supply a 50 MHz data clock from the MCU (RMII) or deal with externally clocked data at 25 MHz (MII)! – Marcus Müller Feb 08 '21 at 23:59
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    It's overkill. I have a SAMD51 running at 120 MHz. Very busy just looping as: read inputs, drive data, read data, drive outputs, repeat. – GaryLa Feb 09 '21 at 00:00
  • how's an upgrade to an SAME5x sound? these things simply do ethernet MAC for you. – Marcus Müller Feb 09 '21 at 00:03
  • Thanks. I'm aware that everything could be changed. I was just asking about using an ethernet phy and transformer to replace a physical layer. – GaryLa Feb 09 '21 at 00:04
  • yeah, no, it's not that easy. I trust you can put that together as soon as you get the clock handling done, and write very time-critical ISRs for some RX data lines, errr. That seems like an unfortunate to spend your time, and 80% chance you'll need some external CPLD/FPGA to do your MAC handling in the end. In which case you'd be back to changing more hardware. – Marcus Müller Feb 09 '21 at 00:06
  • I was thinking about needing a CPLD or similar. It looks like the timing between the MAC and PHY is driven by the Phy (at least some of it), so bit-banging would be challenging. Thanks for your input. – GaryLa Feb 09 '21 at 00:09
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    You don't bit bang Ethernet on a microcontroller. Well, unless you want to have any cycles left over to do anything other than bit banging. Get a part with an actual Ethernet MAC if you want to use Ethernet. – alex.forencich Feb 09 '21 at 01:23
  • I didn't mean literally bit-banging, I just meant recreating the MAC-to-PHY interface using a combination of SPI or QSPI or making a parallel port, etc. And I don't need to do anything else other than sample some inputs, drive some outputs, and communicate with the same board doing the same thing 20 feet away. Using ethernet as is would not work. With 6+6+4+4+20+4+interspacing as the smallest practical packet size, 100Mbps ethernet would be worse than the RS422 is now. I have 2 bytes to send and receive. – GaryLa Feb 09 '21 at 14:16

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