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While studying forwarding in RiscV cpu I saw the following claim:

enter image description here

But I can't understand why we can't do forward in this case, why in different conditions we were able to do this and now we can't?

It was mentioned that the reason is that clock time isn't enough which I don't understand.

Why the reason isn't the fact that we can't forward something that isn't calculated yet?

daniel
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    I think you're confusing a few thing: this isn't specific to your CPU, which is only one implementation of many of the RISC-V instruction set architecture, it's not even specific to RISC-V as you say in your title, this is a logical problem of causality: If an operation takes more than one cycle to complete, you don't have a result in the next cycle. Hence, you can't use that result in the next cycle. – Marcus Müller Jan 27 '21 at 10:36
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    Just think about the temporal sequence of those two red circles... You can forward something that's being calculated the cycle before it's used; but not something that's being calculated while (after) it's used. –  Jan 27 '21 at 12:07
  • so my explanation is correct? @BrianDrummond – daniel Jan 27 '21 at 12:17
  • @daniel Did you lose marks on an exam for your answer? – Elliot Alderson Jan 27 '21 at 13:30
  • @ElliotAlderson didn't do exam yet :) so I don't know if it's correct or not – daniel Jan 27 '21 at 17:51
  • This is a good question to ask your instructor. You want to be sure that you can give the answer that they are looking for. There may be some context to this question that we are not aware of. – Elliot Alderson Jan 27 '21 at 17:55

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