I am trying to work out what the RC network in the circuit below does and how it works. The circuit output is fed as input to a CD4060 binary counter. According to what I have read, the signal from the crystal into the CD4060 must be bounce-less and noise free. Is that what the RC network is doing? How does it work?
10M provides the DC input self-centering bias so the CMOS can amplify the signal near Vdd/2 by virtue of negative feedback from the internal CMOS inverter.
The two C’s are designed to match the crystal load rating for centre frequency. (C1//C2)
The 33k reduces the current so that the internal crystal lattice only draws <50uW due to the high density of power limitations on the crystal lattice inside. It does not affect the frequency and the voltage gain in the CMOS now working as an analog amplifier that limits to a square wave.
Very often, a crystal is operated at one of this resonant frequencies - however, not in this case !! Outside the frequencies for series- or parallel resonance the crystal can work as a capacitor or as a high-Q inductor Lq. The latter applies in the shown example.
As a consequence, we have a frequency-dependent feedback circuit which produces at a certain frequency 180deg phase shift which is necessary to fulfill the oscillation condition. (unity loop gain).
Verification: We have a 3rd-order lowpass in classical ladder structure:
33k-32pF-Lq-15pF.
The maximum phase shift is (for very large frequencies) -270 deg and there is one single frequency with a phase shift of -180deg. (as required).
As explained by Tony Stewart, the 10megohm resistor provides negative DC feedback for operational point stabilization.
