How I can enable and disanable a verilog module

Question

I have two modules. I want to run these modules in order.

This is first module:

module SinusLut(clk, aci ,reset,sonuc);


input reset;
input [7:0]aci;
output reg [15:0]sonuc;
input clk;





always@(posedge clk) begin


    if (reset)
    sonuc<= 'd0;
    
    else begin

    case(aci)
    
        'd1 : sonuc  <= 16'b0000000000010001;
        'd2 : sonuc  <= 16'b0000000000100011;
        'd3 : sonuc  <= 16'b0000000000110101;
        'd4 : sonuc  <= 16'b0000000001000111;
        'd5 : sonuc  <= 16'b0000000001011001;
   endcase
  end 
  end
endmodule

This is second module:

 module CosLut(clk, aci ,reset,sonuc);
    
    
    input reset;
    input [7:0]aci;
    output reg [15:0]sonuc;
    input clk;
    
    
    
    always@(posedge clk)begin 
    
    if(reset)
        sonuc <= 'd0;
    
    else begin 
            
            case(aci)
            
                'd1 : sonuc <= 16'b0000001111111111;
                'd2 : sonuc <= 16'b0000001111111111;
                'd3 : sonuc <= 16'b0000001111111110;
                'd4 : sonuc <= 16'b0000001111111101;
                'd5 : sonuc <= 16'b0000001111111100;
     endcase
      end
      end
    endmodule

And I create two different top module and tried both. Both of them didn't work.

First one:

module TopModule(clk, aci ,reset,sonuc,en,en2);


input en,en2;
input reset;
input [7:0]aci;
output reg [15:0]sonuc;
input clk;




CosLut CosinusLookUp(

.reset(reset),
.aci(aci),
.sonuc(sonuc),
.clk(clk)
);


SinusLut SinusLookUp(

.reset(reset),
.aci(aci),
.sonuc(sonuc),
.clk(clk)
);


always@(posedge clk ) begin

if (en2==1) begin

SinusLut;

end

else begin

CosLut;

end
end

endmodule

Second one:

 module TopModule(clk, aci ,reset,sonuc,en,en2);
    
    
    input en,en2;
    input reset;
    input [7:0]aci;
    output reg [15:0]sonuc;
    input clk;
    
    
    always@(posedge clk) begin
    
    if(en2) begin

    CosLut CosinusLookUp(
    
    .reset(reset),
    .aci(aci),
    .sonuc(sonuc),
    .clk(clk)
    );
    
    end 

    else begin 

    SinusLut SinusLookUp(
    
    .reset(reset),
    .aci(aci),
    .sonuc(sonuc),
    .clk(clk)
    );

    end

end 
endmodule

Basically I want to enable first module after sometime i want to disenable it and enable other one.

Thank you in advance.

You can't use Verilog as a general purpose programming language. An HDL is a **hardware** description language. You can not control the order of execution of modules or blocks. — Elliot Alderson, Jan 19 '21 at 14:09

alex.forencich · Answer 1 · 2021-01-20T07:41:45.850

Most likely what you want to do is instantiate both modules and then select the output that you want and ignore the output that you don't want.

Something along these lines:

module TopModule(
    input wire clk,
    input wire reset,
    input wire [7:0] aci,
    input wire sel,
    output wire [15:0] sonuc
);
    
    wire [15:0] sonuc1, sonuc2;
    
    assign sonuc = sel ? sonuc1 : sonuc2;
    
    CosLut CosinusLookUp(
        .clk(clk),
        .reset(reset),
        .aci(aci),
        .sonuc(sonuc1)
    );

    SinusLut SinusLookUp(
        .clk(clk),
        .reset(reset),
        .aci(aci),
        .sonuc(sonuc2)
    );
    
endmodule

How I can enable and disanable a verilog module

1 Answers1