I'm having difficulties in understanding this statement from "The Art of Electronics 3rd Edition".
I don't understend how they estimated the MOSFET's switching time using the gate current and the feedback capacitance.
Here is the quote:
As another example, imagine switching a 5 amp highvoltage load with a power MOSFET (there aren’t any highpower JFETs), in the style of Figure 3.50. One might naively assume that the gate could be driven from a digital logic output with low current-sourcing capability, for example the so-called 4000-series CMOS logic, which can supply an output current of the order of 1mA with a swing from ground to +10V. In fact, such a circuit would be a disaster, because 1mA of gate drive into the 200 pF average feedback capacitance of the IRF740 would stretch the output switching speed to a leisurely 50μs.