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I'm using the Lattice Diamond licensed version of Aldec Active-HDL. The logic circuits I'm working with are complex enough that I believe propagation delays could have an impact on the actual function of the hardware.

Is there a way to enable a propagation delay in simulation? Or a generic Verilog way of introducing a delay like this?

Gacekky1
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1 Answers1

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Yes. In Verilog you use the # operator to introduce delays in simulation. This is well documented on many web sites.

Elliot Alderson
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  • Not a delay, a propagation delay based on the number of gates used, etc. I suppose adding a delay to every gate instantiation would work, but not for higher level code. – Gacekky1 Jan 14 '21 at 22:02
  • You can add delays for any kind of assignment, you don't have to instantiate every gate. Your question didn't say anything about "delay based on the number of gates". – Elliot Alderson Jan 15 '21 at 00:56